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october 2007 revision: eb17_01.4 latticemico32/dsp development board user? guide
2 latticemico32/dsp development board lattice semiconductor user? guide introduction this document describes the features and functionality of the latticemico32/dsp development board. this board is designed as a hardware platform for design and development with the latticemico32 microprocessor, as well as for the latticemico8 microcontroller, and for various dsp functions. this document describes the numerous functional elements of the board. the schematics of the board can be found in the appendix at the end of this document. features latticeecp fpga with 33,800 lut4s, 131 kbit of embedded ram, 4 plls, and 360 user i/o pins lattice machxo with 640 luts serial flash with 8 mbit for non-volatile storage of fpga con?uration data. ddr sodimm socket for ddr sdram modules (ddr1, 100-133mhz, 32-bit data bus) parallel flash 2x128 mbit, organized as 8m 32-bit words sram 2x4 mbit, organized as 256k 32-bit words usb 2.0 connector and integrated ispdownload cable for programming the fpga flywire connector for programming using an ispdownload cable (available separately) 9-pin rs232 serial port (230 kbps) 15-pin vga (64 color encoding) ethernet 10/100 m full/half duplex two usb 2.0 compatible host connectors one usb 2.0 compatible target connector one usb otg (on-the-go) connector expansion connector with 46 user i/os 12x12 prototyping area for the integration of individual components (connections to the fpga) 8x6 prototyping area for the integration of individual components (connections to the machxo) sigma delta d/a converter crimp connector with 5 signal pairs for high-speed data transfer audio interface (line-in, line-out, and microphone) codec lcd connector for character displays, with contrast potentiometer 25 mhz oscillator with clock distribution buffer eight leds with test points for each led two-character 7-segment display green led to indicate the proper operation of the 3.3v and 2.5 v power supplies blue led which shows the con?uration status (?one? red led to signal that the fpga can be con?ured (?nit? yellow led indicating the fpga program# i/o is asserted (?rogram#? 3x4 key matrix
3 latticemico32/dsp development board lattice semiconductor user? guide four dip switches single step key program key to initiate the con?uration sequence of the fpga reset key 5v power supply switching regulator for the generation of the 3.3v i/o voltage, the 2.5v ddr and lvds voltages and the 1.2v core voltage getting started 1. unpack all components and compare them to the packaging list. all boards leave the factory fully tested. detailed information can be found in the troubleshooting section of this document. 2. place the board in front of you so that the keyboard is on the left side. 3. take the regulated dc power supply which has been supplied with the package and connect it to the power jack on the board. two green power-on leds will illuminate to con?m that power is correctly applied to the board (regulating 5v to 3.3v and 2.5v). 4. to check the basic functionality, please see the troubleshooting section of this document. a number of example and demonstration programs are available for the latticemico32/dsp development board. check the lattice web site at: www .latticesemi.com/boards (and navigate to the correct board) to ?d additional documentation, and design and programming ?es. note: unless described otherwise, positional statements (left, right etc.) refer to the board positioned in front of you so that the key pad is in the bottom left corner. related literature latticemico32 development kit users guide : this guide includes a tutorial for using the latticemico32 sys- tem software with the latticemico32/dsp development board. latticemico32/dsp demonstration : this includes a documented demonstration of a dsp example using the latticemico32/dsp development board. these documents can be downloaded from the lattice web site at: www .latticesemi.com/boards . select the fpga/fpsc boards -> latticemico32/dsp development board and click on the user manuals link. overview the following block diagram gives you an overview of the functionality of your latticemico32/dsp development board. subsequent pages illustrate the position of connectors, user interfaces, and modules.
4 latticemico32/dsp development board lattice semiconductor user? guide figure 1. latticemico32/dsp development board block diagram table 1. board defaults peripheral interfaces this section describes all peripheral interfaces of the latticemico32/dsp development board in alphabetical order. figure 2 shows the position of peripheral interfaces available on the board. item type default status comments latticeecp33 fpga programmed the bitstream is based on example platforma and the led7segstest project. the led7segstest.mem and led7segstest.bit ?es are included in the led7segstest project. visual indications of operation are: ? left to right and right to left scanning of the 8 leds. ? upcount and roll over of the 7 segment displays from 0 to 99 decimal at ~1 second intervals. lcd backlight (x5) jumper open backlight is off. con?uration switch tms switch off (down) latticeecp33 device can be programmed. sigma delta dac converter jumper open contrast control reostat varible not set to any speci? level. 4-place dip - logic 1 switch off logic 0 on selected pins - see table 18. sodimm ddr 400 setting (x18) jumper shorts pins 1 and 2 set to below ddr400 memory use.
5 latticemico32/dsp development board lattice semiconductor user? guide figure 2. peripheral interfaces audio interface the audio interface has two connectors for 3.5 mm stereo jacks. the upper one is for line-out, the lower for line-in. they are connected to the audio codec tlv320aic23bipw from texas instruments. lcd contrast potentiometer microphone inp u t a u dio line in line o u t lcd connector x6 ethernet 10/100m 3.3 v testpoint 2.5 v testpoint g n d testpoint 1.2 v testpoint clk testpoint fly w ire- connector x3 high-speed usb for config u ration dip-s w itch for the config u ration x5 x13 x12 expansion connector ddr sdram socket x4 usb host connector mini usb otg-connector po w er pl u g rs232 x1a v ga x1b sigma delta dac connector
6 latticemico32/dsp development board lattice semiconductor user? guide table 2. audio codec u1001 pin de?itions the signal codec cs# has a pull-up resistor of 10 k . the signal codec mode selects the interface to use for the codec. driving it high corresponds to spi, low to i 2 c. detailed information on the audio codec can be found at the texas instruments web site at www .ti.com . clock sources a 25 mhz oscillator supplies the fpga (primary clock pin a10 and pll input v1), the machxo (pin a8), the ether- net controller and the expansion connector (pin 29 of x12). the frequency can be measured via testpoint clk. a 25mhz input clock is required by the ethernet controller. to generate other clock frequencies, use the plls of the fpga. you can ?d detailed information for the usage of the plls on the lattice web site and in the latticeecp/ec family data sheet. the usb controller requires a 24 mhz quartz oscillator for con?uration. another 12 mhz quartz supplies the usb host/peripheral controller. ddr sodimm socket for ddr sdram modules the board includes a standard ddr1 sodimm socket with 200 contacts (ddr sdram module is not included). the upper four bytes of the data bus are not connected. thus, only half of the capacity of the memory module is available. the ddr sodimm socket is factory con?ured to provide a regulated 2.5v. ddr400 modules require a power supply of 2.6v (?.1v). to support ddr400, you must short-circuit pins 2 and 3 of connector x18. position 1-2 is used for 2.5v mode. if you have your board in front of you so that the power supply is in the upper left corner, pin 1 is the right-most one and is marked with a copper etched triangle . note:in bank 2, there are four dqss. two of them do not have the required dq pins available. therefore, only two ddr interfaces are valid. so, the latticeecp33 can have a 16-bit ddr interface . pin signal name fpga pin pin signal name fpga pin 3 codec bclk w1 21 codec cs# w4 4 codec din w2 6 codec dout w3 5 codec lrcin aa1 7 codec lrcout y2 25 codec mclk y3 24 codec sclk y1 23 codec sdin aa2 22 codec mode v4 table 3. ddr sodimm socket (x4) - data bus, n.c. ... not connected pin signal name fpga pin pin signal name fpga pin 11 ddr dqs0 a16 47 ddr dqs2 h18 12 ddr dm0 b15 48 ddr dm2 h19 5 ddr dq0 a14 41 ddr dq16 d21 7 ddr dq1 b14 43 ddr dq17 f20 13 ddr dq2 a15 49 ddr dq18 g21 17 ddr dq3 b16 53 ddr dq19 g20 6 ddr dq4 a17 42 ddr dq20 h20 8 ddr dq5 b17 44 ddr dq21 j19 14 ddr dq6 a18 50 ddr dq22 j18 18 ddr dq7 b18 54 ddr dq23 h17 25 ddr dqs1 d21 61 ddr dqs3 j20 26 ddr dm1 d21 62 ddr dm3 k20
7 latticemico32/dsp development board lattice semiconductor user? guide table 4. ddr sodimm socket (x4) - address bus table 5. ddr sodimm socket (x4) - other signals ethernet interface an intel lxt971a is included for ethernet phy. this is an ieee-compliant fast ethernet phy transceiver that directly supports both 100base-tx and 10base-t applications, full and half duplex. for more information, please refer to the data sheet of this component. table 6. ethernet controller u0801 pin de?ition 19 ddr dq8 b22 55 ddr dq24 f22 23 ddr dq9 b21 59 ddr dq25 g22 29 ddr dq10 c21 65 ddr dq26 h22 31 ddr dq11 c22 67 ddr dq27 h21 20 ddr dq12 e20 56 ddr dq28 k19 24 ddr dq13 e18 60 ddr dq29 k18 30 ddr dq14 f19 66 ddr dq30 l18 32 ddr dq15 f18 68 ddr dq31 l19 pin signal name fpga pin pin signal name fpga pin 112 ddr a0 d16 111 ddr a1 c16 110 ddr a2 e15 109 ddr a3 d15 108 ddr a4 c15 107 ddr a5 e14 106 ddr a6 d14 105 ddr a7 c14 102 ddr a8 e13 101 ddr a9 d13 115 ddr a10 e16 100 ddr a11 c13 99 ddr a12 b13 123 ddr a13 c17 117 ddr ba0 e17 116 ddr ba1 d17 pin signal name fpga pin pin signal name fpga pin 35 ddr ck0+ b12 37 ddr ck0- a12 160 ddr ck1+ a20 158 ddr ck1- b19 96 ddr cke0 a13 95 ddr cke1 c12 118 ddr ras# c18 119 ddr we# d18 120 ddr cas# a19 121 ddr s0# c19 pin signal name fpga pin pin signal name fpga pin 4 hpe resout# h6 42 eth mdio k4 43 eth mdc k5 45 eth rxd3 f2 46 eth rxd2 g3 47 eth rxd1 g2 48 eth rxd0 g1 49 eth rxdv j4 52 eth rxclk k1 53 eth rxer j5 54 eth txer j2 55 eth txen j3 56 eth txclk j1 57 eth txd0 h1 58 eth txd1 h2 59 eth txd2 h3 60 eth txd3 h4 62 eth col k2 63 eth crs k3 64 eth mdintr# f1 table 3. ddr sodimm socket (x4) - data bus, n.c. ... not connected (continued)
8 latticemico32/dsp development board lattice semiconductor user? guide expansion connector the expansion connector provides 46 user i/os connected to the fpga. the remaining pins serve as power and clock supplies for expansion boards. the expansion connector is con?ured as two 2x20 100mil centered pin head- ers (x12 and x13). tables 7 and 8 describe the connections to the fpga. table 7. expansion connector x12 pin signal name fpga pin pin signal name fpga pin 1 gnd 2 n.c. (coding) 3 vcc2v5 4 expcon io29 w21 5 expcon io30 w20 6 expcon io31 w19 7 expcon io32 y20 8 expcon io33 aa22 9 expcon io34 aa21 10 expcon io35 ab21 11 expcon io36 t17 12 expcon io37 t14 13 expcon io38 t13 14 expcon io39 u14 15 expcon io40 u13 16 expcon io41 u12 17 expcon io42 u11 18 expcon io43 v14 19 expcon io44 v13 20 expcon io45 w13 21 vcc5v0 22 gnd 23 vcc2v5 24 gnd 25 vcc3v3 26 gnd 27 vcc3v3 28 gnd 29 expcon osc 30 gnd 31 expcon clkin 32 gnd 33 expcon clkout 34 gnd 35 vcc3v3 36 gnd 37 vcc3v3 38 gnd 39 vcc3v3 40 gnd table 8. expansion connector x13 pin signal name fpga pin pin signal name fpga pin 1 hpe reset# 2 gnd 3 expcon io0 k22 4 expcon io01 k21 5 expcon io2 l22 6 expcon io03 l21 7 expcon io4 l20 8 expcon io05 m22 9 expcon io6 m21 10 expcon io07 m20 11 expcon io8 m19 12 expcon io09 m18 13 expcon io10 n22 14 expcon io11 n21 15 expcon io12 n20 16 expcon io13 n19 17 expcon io14 n18 18 expcon io15 p22 19 gnd 20 vcc3v3 21 expcon io16 p21 22 gnd 23 expcon io17 p20 24 gnd 25 expcon io18 p18 26 gnd 27 expcon io19 p19 28 expcon io20 r22 29 expcon io21 r21 30 gnd 31 expcon io22 r19 32 expcon io23 r18
9 latticemico32/dsp development board lattice semiconductor user? guide ispdownload cable connector there are two ways to con?ure the programmable lattice devices on the board. the usb connector requires a standard usb cable, and is described later in this document. connector x3 is available to connect a lattice isp- download cable. an ispdownload cable is used to program ieee 1532 compliant programmable devices. lattice provides either a parallel port or a usb port download cable. the fpga and cpld are programmed using the cable and ispvm programming software. dip switch sw0302 1 controls the device to be con?ured: the fpga or the machxo. if it is on (in top position), the machxo is selected; if off, the fpga is selected. the ispvm system software can be downloaded from the lattice web site at: www .latticesemi.com/ispvm . note: do not change the switch when the con?uration of a device is in progress! note: the board as con?ured from the factory, has a built-in usb ispdownload cable. the built-in cable and an external ispdownload cable cannot be used at the same time. table 9. ispdownload connector x3 pin de?ition high-speed lvds connector on the right side of the board there is a 20-pin jack for connecting crimp cables. five lvds signal pairs of the fpga are wired with the connector (see table 10). this interface serves as a means for high-speed data transfer. figure 3. 20-pin df13 connector by hirose 33 expcon io24 r17 34 gnd 35 expcon io25 t22 36 expcon io26 t18 37 expcon io27 u22 38 cardsel# v20 39 expcon io28 v19 40 gnd 1. caption on the board: conf. pin signal name pin signal name 1 vcc3v3 2 jtag_tdo 3 jtag_tdi 4 jtag_prog 5 jtag_trst 6 jtag_tms 7 gnd 8 jtag_tck 9 jtag_done 10 jtag_init table 8. expansion connector x13 (continued)
10 latticemico32/dsp development board lattice semiconductor user? guide table 10. high-speed connector x14 pin de?ition lcd connector (optional) the lcd connector is a 16-pin header with a standard pinning for lcd modules with back-light (e.g. truly mtc- c202dprn-1n). in order to use an lcd module, attach it to the connector via a 16-pin ribbon cable. note: the lcd module is tied to a 5v supply. the latticeecp33 to lcd interface is 3.3v. put a jumper on connector x5 to turn on the backlight of the lcd. the contrast of the lcd module is adjustable with the potentiometer r0526, because different lcd modules need different voltages for the best contrast. figure 4. lcd panel (not included) table 11. lcd connector x6 pin de?ition serial interface the board includes an rs232 serial interface port. the interface provides transmit (tx), receive (rx), and hard- ware handshaking. the maxim max3232 data sheet provides detailed information on the interface circuit. a 9-pin female to 9-pin female null modem cable is required. pin signal name fpga pin pin signal name fpga pin 1 hscon dat0- e21 2 hscon dat0+ d22 3 gnd 4 gnd 5 hscon dat1- g19 6 hscon dat1+ g18 7 gnd 8 gnd 9 hscon dat2- f21 10 hscon dat2+ e22 11 gnd 12 gnd 13 hscon dat3- j22 14 hscon dat3+ j21 15 gnd 16 gnd 17 hscon dat4- g17 18 hscon dat4+ f17 19 gnd 20 gnd pin signal name fpga pin pin signal name fpga pin 1 gnd 2 vcc5v 3 contrast 4 lcd regsel p3 5 lcd rw p4 6 lcd enable p5 7 seg a#/db0 m3 8 seg b#/db1 m4 9 seg c#/db2 m5 10 seg d#/db3 n1 11 seg e#/db4 n2 12 seg f#/db5 n3 13 seg g#/db6 n4 14 seg dp#/db7 n5 15 backlight 16 gnd
11 latticemico32/dsp development board lattice semiconductor user? guide table 12. serial interface x1c pin de?itions sigma delta d/a converter the board includes a low-pass ?ter connected to a dedicated pin of the fpga. with this, a sigma delta converter can be realized. great results can be achieved by using a resolution of 8 to 10 bits. example vhdl code is pro- vided. power supply four different voltages are needed: 3.3v i/o voltage, 2.5v ddr and lvds voltages as well as 1.2v core voltage. the 3.3v supply draws up to 1a, the 2.5v and 1.2v supplies up to 2a of current. for more information, see the power supply information in the components section of this document. test points in order to check the various voltage levels used, several test points are provided. there is one test point for 1.2v, 2.5v, 3.3v, one for ground, and one for accessing the 25mhz oscillator. the 25mhz clock signal can be checked with another test point. usb host/peripheral interface there are one usb peripheral and two usb host connectors on board. these are connected to the cypress cy7c67300 usb host/peripheral controller u0702. this controller is compliant with the universal serial bus speci?ation 2.0. you can transmit and receive serial data at both full-speed (12 mbps) and low-speed (1.5 mbps) data rates. for more information, please refer to the data sheet of the usb controller. u0703 and u0704 are usb power control switches, which must be enabled by the user via the usb pwen signals. the usb oc signal pulls low to indicate voltage, current and thermal issues. table 13. usb gpio connections (u0702) signal direction sub-d pin rs232 function fpga pin rs txd lvttl out 3 transmit data l1 rs rts lvttl out 7 request to send l2 rs rxd lvttl in 2 receive data m2 rs cts lvttl in 8 clear to send m1 pin signal name fpga pin pin signal name fpga pin 94 usb gpio0 b7 93 usb gpio1 c7 92 usb gpio2 d7 91 usb gpio3 e7 90 usb gpio4 f7 89 usb gpio5 a8 87 usb gpio6 b8 86 usb gpio7 c8 66 usb gpio8 d8 65 usb gpio9 e8 61 usb gpio10 f8 60 usb gpio11 a9 59 usb gpio12 b9 58 usb gpio13 c9 57 usb gpio14 d9 56 usb gpio15 e9 55 usb gpio16 f9 54 usb gpio17 g9 53 usb gpio18 b10 52 usb gpio19 c10 50 usb gpio20 d10 49 usb gpio21 e10 48 usb gpio22 f10 47 usb gpio23 g10 46 usb gpio24 b11 45 usb gpio25 c11 44 usb gpio26 d11 43 usb gpio27 e11 42 usb gpio28 e12 41 usb gpio29 pulled up
12 latticemico32/dsp development board lattice semiconductor user? guide table 14. additional usb gpio connections (u0702, u0704, and u0704) usb con?uration connector in addition to the ispdownload connector, the fpga and the machxo can also be con?ured by a standard usb connection. the usb target connector is wired to the cypress cy7c68013a device (u0301). this programming method requires the use of the ispvm system software. this can be downloaded from the lat- tice web site at: www .latticesemi.com/ispvm . this connection will appear to the ispvm system software as if a regular usb-based ispdownload cable is con- nected to the pc. the cy7c68013a in combination with the machxo cpld acts as a built-in ispdownload cable. the machxo is connected to the ispdownload connector x3, and can program the latticeecp33. the latticeecp33 can be programmed when dip switch sw0302 is ?ff (pushed down). note: like the ispdownload connector, the machxo drives the jtag signals when it is programmed for usb con?uration. only use the built-in ispdownload cable or an external ispdownload cable exclusively. it is not recommended to switch between cables without ?st power cycling the board. failure to follow this recommenda- tion may cause unpredictable results and may possibly damage the board. pin signal name fpga pin pin signal name fpga pin u0703:1 usb pwen0 b2 u0703:2 usb oc0# e1 u0703:4 usb pwen1 c2 u0703:3 usb oc1# d1 u0704:1 usb pwen2 c3 u0704:2 usb oc2# d2 u0702:85 hpe resout# b3 table 15. connections between the usb controller (cy7c68013a) and the machxo device cypress pin signal name machxo pin cypress pin signal name machxo pin 34 gp d0 g14 35 gp d1 g13 36 gp d2 h14 37 gp d3 h13 44 gp d4 h12 45 gp d5 j13 46 gp d6 j12 47 gp d7 k14 80 gp d8 k13 81 gp d9 k12 82 gp d10 l14 83 gp d11 m13 95 gp d12 m14 96 gp d13 m12 97 gp d14 n14 98 gp d15 n13 57 gp adr0 h1 58 gp adr1 h2 59 gp adr2 j1 60 gp adr3 j3 61 gp adr4 k1 62 gp adr5 k2 63 gp adr6 l1 64 gp adr7 l3 93 gp adr8 m1 69 gp sloe m3 67 gp int0 n7 68 gp int1 m6 71 gp fifoadr0 m4 72 gp fifoadr1 n4 70 gp wu2 n3 73 gp pktend p5 74 gp slcs# e3 79 usbcf wake n9 3 gp rdy0 d3 4 gp rdy1 e2 5 gp rdy2 f2 6 gp rdy3 f3 7 gp rdy4 g1 8 gp rdy5 g2 54 gp ctl0 d1 55 gp ctl1 c3
13 latticemico32/dsp development board lattice semiconductor user? guide vga interface the board includes a vga connector for driving a vga monitor. the vga interface is connected to a 15-pin plug socket. the pin de?itions are listed in table 16. vga rd0 and vga rd1 are both connected to pin 1, but have different series resistors (see figure 5). thus, a 6- bit vga interface is realized. figure 5 shows the connection of the rgb signals. the fpga is responsible for gen- erating correct hsync and vsync sweep frequencies. understand the sync frequencies of the vga monitor being connected to the vga plug and adjust the fpga frequencies as required. table 16. vga connector x1b pin de?ition, n.c. ... not connected figure 5. vga connector 56 gp ctl2 c2 51 gp ctl3 c1 52 gp ctl4 b2 76 gp ctl5 b1 23 gp t0 m2 24 gp t1 n1 25 gp t2 p1 28 gp bkpt f12 100 usb clk o m7 26 gp ifclk m8 41 gp rxd0 e13 40 gp txd0 e14 43 gp rxd1 f13 42 gp txd1 f14 pin signal name fpga pin pin signal name fpga pin 1 vga rd0 a3 1 vga rd1 b4 2 vga gr0 a4 2 vga gr1 b5 3 vga bl0 a5 3 vga bl1 b6 4 n.c. 5 n.c. 6 gnd 7 gnd 8 gnd 9 n.c. 10 gnd 11 n.c. 12 n.c. 13 vga hsync a7 14 vga vsync a6 15 n.c. table 15. connections between the usb controller (cy7c68013a) and the machxo device (continued)
14 latticemico32/dsp development board lattice semiconductor user? guide user interface figure 6 shows the position of the user interface elements. figure 6. user interface features 2.5 v led (green) 3.3 v led (green) fpga config u ration led ( b l u e) fpga initialization led (red) single-step key reset key 3 x 4 key b oard 7-segment display 8 leds w ith testpads lcd connector program key program led (yello w ) 4 x dip s w itches
15 latticemico32/dsp development board lattice semiconductor user? guide 7-segment display the 7-segment display is wired as follows: table 17. 7 segment display u0502 pin de?ition the signals of the 7-segment display are low-active, which means that with a logic ?? the segment is lit. seg a# ... seg f# and seg dp# drive not only the two 7-segment displays, but also the lcd. to write different data to these three components, the user must drive the signals alternately to the components. this can be realized with the sig- nals seg ca0#, seg ca1# and lcd enable. they serve to activate the two 7-segment displays and the lcd, respectively. dip switches there is a 4-bit dip switch on the board. when the switch is turned to the on position, a logic ? will be seen. the connections are in table 18. table 18. dip switches sw0514 connection leds eight leds can be used for custom status signaling. they are low-active; with a logic ? the led is on. you can control the leds via the signals below. table 19. led ld0501 ... ld0508 connection pin signal name fpga pin pin signal name fpga pin a sed_a# m3 e sed_e# n2 b sed_b# m4 f sed_f# n3 c sed_c# m5 g sed_g# n4 d sed_d# n1 d, p sed_dp# n5 left sed_ca0# p1 right sed_ca1# p2 common common switch signal name fpga pin switch signal name fpga pin sw315 sw316 1 dsw0 r2 2 dsw1 r3 3 dsw2 r4 4 dsw3 r5 pin signal name fpga pin pin signal name fpga pin 1 led0# e3 5 led4# f5 2 led1# e4 6 led5# g4 3 led2# e5 7 led6# g5 4 led3# f4 8 led7# h5 a b c d e f g
16 latticemico32/dsp development board lattice semiconductor user? guide key matrix the board also features a key matrix with 12 push-buttons, which are not debounced. they must be driven with three column lines and can be read with four rows. the following table shows the connections. table 20. key matrix with the keys sw302 ... sw313 de?ition table 21. key matrix with the keys sw302 ... sw313 connection to query all keys of the matrix, you must poll the column driver signals (tst col0, tst col1, and tst col2). if you press a key, a logic ? appears in the corresponding row. the following diagram explains the functionality: figure 7. polling of the key matrix you do not need the polling method if only four keys are used. connect the column driver signals of one column to vcc, the other two to gnd and query the row data signals. cpu reset key the cpu reset key is a global reset. please refer to the reset chip section of this document for detailed informa- tion. single step key the single step key is connected to a normal input of the fpga and can be used by the application as required. this key is connected to a schmitt trigger, meaning it is debounced. this key is used as a single clock for testing your design. signal name tst_col0 tst_col1 tst_col2 tst_row0 1 2 3 tst_row1 4 5 6 tst_row2 7 8 9 tst_row3 c 0 e signal name fpga pin signal name fpga pin tst_row0 t1 tst_col0 u4 tst_row1 t2 tst_col1 u6 tst_row2 t3 tst_col2 v5 tst_row3 r1 col0 col1 col2 ro w 0 ro w 1 1 pressed 3 pressed 6 pressed 6 pressed
17 latticemico32/dsp development board lattice semiconductor user? guide components figure 8 illustrates the position of major components. figure 8. components ethernet phy asynchrono u s sram spi flash machxo a u dio codec usb controller usb controller for the config u ration 8 x 6 prototyping area of the machxo parallel flash 12 x 12 prototyping area of the fpga fpga lfec33
18 latticemico32/dsp development board lattice semiconductor user? guide 12 x 12 fpga prototyping area of the fpga a 12x12 prototyping area is available on the right side of the board. the lead-wire spacing of the prototyping area is 100mil (2.54 mm). figure 10 shows the prototyping area in top view. 14 plated-through-holes on its left side are connected to the fpga. eight through-holes on the right side are wired to a 2.5v i/o bank. in the top row of the prototyping area there are six connections to the 3.3v power supply as well as three to 2.5v. the bottom row has ten plated-through-holes connected to gnd. table 22. fpga connections for the 12x12 prototyping area fpga pin signal name lrf pin fpga pin signal name lrf pin ab13 bb3v3 io0 tp0901 ab12 bb3v3 io1 tp0902 aa12 bb3v3 io2 tp0903 y12 bb3v3 io3 tp0904 w12 bb3v3 io4 tp0905 v12 bb3v3 io5 tp0906 v11 bb3v3 io6 tp0907 u10 bb3v3 io7 tp0908 t10 bb3v3 io8 tp0909 u9 bb3v3 io9 tp0910 t9 bb3v3 io10 tp0911 u8 bb3v3 io11 tp0912 ab10 bb3v3 clk0+ tp0918 ab11 bb3v3 clk0- tp0919 f11 bb2v5 io0 tp09133 f12 bb2v5 io1 tp09134 f13 bb2v5 io2 tp09135 g13 bb2v5 io3 tp09136 f14 bb2v5 io4 tp09137 g14 bb2v5 io5 tp09140 f15 bb2v5 io6 tp09141 f16 bb2v5 io7 tp09142 vcc3v3 tp0913 vcc3v3 tp0925 vcc3v3 tp0937 vcc3v3 tp0949 vcc3v3 tp0961 vcc3v3 tp0973 vcc2v5 tp0997 vcc2v5 tp09109 vcc2v5 tp09121 gnd tp0924 gnd tp0936 gnd tp0948 gnd tp0960 gnd tp0972 gnd tp0984 gnd tp0996 gnd tp09108 gnd tp09120 gnd tp09132
19 latticemico32/dsp development board lattice semiconductor user? guide figure 9. schematic illustration of the prototyping area 8 x 6 machxo prototyping area there is a second prototyping area connected to the machxo. its lead-wire spacing is also 100mil (2.54 mm). 22 drill holes are connected to the machxo. the topmost row is connected to the 3.3v power supply; the bottom-most to ground. table 23. machxo connections for the 8x6 prototyping area machxo pin signal name lrf pin machxo pin signal name lrf pin a6 aa3v3 io0 tp0307 b6 aa3v3 io1 tp0313 c6 aa3v3 io2 tp0319 b7 aa3v3 io3 tp0325 b8 aa3v3 io4 tp0331 b14 aa3v3 io5 tp0337 b10 aa3v3 io6 tp0332 c10 aa3v3 io7 tp0326 a11 aa3v3 io8 tp0320 c11 aa3v3 io9 tp0314 a12 aa3v3 io10 tp0308 b12 aa3v3 io11 tp0311 b12 aa3v3 io12 tp0311 a13 aa3v3 io13 tp0323 b13 aa3v3 io14 tp0329 a14 aa3v3 io15 tp0335 c14 aa3v3 io16 tp0342 c13 aa3v3 io17 tp0336 d12 aa3v3 io18 tp0330 d14 aa3v3 io19 tp0324 n6 aa3v3 io20 tp0318 g3 aa3v3 io21 tp0312 vcc3v3 tp0301 vcc3v3 tp0302 vcc3v3 tp0303 vcc3v3 tp0304 vcc3v3 tp0305 vcc3v3 tp0306 bb3 v 3_io[11:0] bb3 v 3_clk0- bb3 v 3_clk0+ bb3 v 3_io3 bb3 v 3_io2 bb3 v 3_io1 bb3 v 3_io0 bb3 v 3_io4 bb3 v 3_io5 bb3 v 3_io6 bb3 v 3_io7 bb3 v 3_io 8 bb3 v 3_io9 bb3 v 3_io10 bb3 v 3_io11 bb2 v 5_io0 bb2 v 5_io[9:0] bb2 v 5_io1 bb2 v 5_io2 bb2 v 5_io3 bb2 v 5_io4 bb2 v 5_io6 bb2 v 5_io7 bb2 v 5_io 8 bb2 v 5_io9 bb2 v 5_io5 bb2 v 5_dat0- bb2 v 5_dat0+ v cc3 v 3 g n d v cc2 v 5 tp09104 tp0935 tp0996 tp0912 tp0963 tp09124 tp0954 tp09117 tp0944 tp090 8 tp09106 tp0936 tp0921 tp0964 tp09 8 6 tp09125 tp0957 tp09115 tp0946 tp09107 tp09135 tp0926 tp0965 tp09 8 5 tp09126 tp0955 tp0920 tp09116 tp0947 tp0910 8 tp0909 tp0975 tp09136 tp0925 tp0966 tp09129 tp0934 tp0956 tp0911 8 tp094 8 tp0976 tp099 8 tp09137 tp0969 tp0922 tp09127 tp095 8 tp0903 tp09119 tp093 8 tp0977 tp09133 tp0910 tp0913 8 tp0967 tp0912 8 tp0901 tp0959 tp09 8 7 tp09120 tp0937 tp0923 tp097 8 tp09141 tp096 8 tp09130 tp0927 tp0960 tp0904 tp09 88 tp09110 tp09 8 1 tp0911 tp09139 tp0970 tp0924 tp09131 tp092 8 tp0950 tp09121 tp0915 tp09 8 9 tp0979 tp09140 tp0971 tp0999 tp09132 tp0929 tp0949 tp0990 tp09 8 0 tp0914 tp09142 tp0939 tp0972 tp0916 tp09100 tp0905 tp09122 tp0930 tp0993 tp09 8 2 tp09143 tp0940 tp0962 tp09109 tp09101 tp0933 tp0913 tp0991 tp0917 tp09 8 3 tp0902 tp09111 tp09144 tp0941 tp0961 tp09102 tp0906 tp0931 tp0992 tp09 8 4 tp0951 tp09112 tp09134 tp0942 tp09105 tp091 8 tp0932 tp0994 tp0952 tp0974 tp0997 tp09113 tp0945 tp09103 tp0907 tp0995 tp09123 tp0953 tp0919 tp0973 tp09114 tp0943
20 latticemico32/dsp development board lattice semiconductor user? guide figure 10. schematic illustration of the prototyping area asynchronous sram the board is populated with two asynchronous k6r4016v1d-tc10 srams from samsung. every one of them is 4 mbit in size with a data bus width of 16 bits. they are wired as one memory with a 32-bit data bus and a depth of 256 k. the 18-bit address bus, the data bus and the control signals are connected directly to the fpga. machxo the lcmxo640 is a non-volatile, instant-on, reprogrammable logic device. it supports ?ackground programming (i.e., the device can be programmed while in operation). the machxo comes preprogrammed from the factory. the factory program permits the cy7c68013a/machxo combination to work as a built-in usb ispdownload cable. using ispvm software the built-in download cable permits the fpga, and spi prom, to be programmed. it is not recommended for the machxo to be repro- grammed. however, the machxo does provide some connections to the latticeecp33 fpga, and to an 8x6 proto- typing area. for further information, please consult the machxo family data sheet. gnd tp0343 gnd tp0344 gnd tp0345 gnd tp0346 gnd tp0347 gnd tp0348 table 23. machxo connections for the 8x6 prototyping area (continued) aa3 v 3_io1 aa3 v 3_io21 aa3 v 3_io20 aa3 v 3_io19 aa3 v 3_io2 aa3 v 3_io3 aa3 v 3_io0 aa3 v 3_io1 8 aa3 v 3_io7 aa3 v 3_io 8 aa3 v 3_io9 aa3 v 3_io10 aa3 v 3_io11 aa3 v 3_io12 aa3 v 3_io13 aa3 v 3_io14 aa3 v 3_io4 aa3 v 3_io17 aa3 v 3_io6 aa3 v 3_io15 aa3 v 3_io5 aa3 v 3_io16 v cc3 v 3 g n d tp0319 tp031 8 tp0337 tp0332 tp0303 tp0325 tp0324 tp033 8 tp0333 tp0310 tp0343 tp0330 tp0339 tp0334 tp0316 tp0301 tp034 8 tp0340 tp0335 tp0322 tp030 8 tp0306 tp0341 tp0336 tp032 8 tp0314 tp0342 tp0346 tp0320 tp0304 tp0326 tp0311 tp0344 tp0317 tp0302 tp0323 tp0309 tp0329 tp0327 tp0347 tp0315 tp0307 tp0305 tp0321 tp0313 tp0312 tp0331 tp0345
21 latticemico32/dsp development board lattice semiconductor user? guide table 24. interface between the machxo and the fpga fpga the lfecp33 represents the heart of the board. it has the following features: 32.8 k look-up tables (luts) 131 kbit distributed ram 498 kbit ebr sram 54 ebr sram blocks four plls 360 user i/os available ddr memory support (ddr400) supported i/o standards: lvcmos, lvttl, sstl, hstl, lvds the isplever design software can be used to develop/modify programs for the fpga using verilog or vhdl design entry methods. for more information on the isplever software, see www .latticesemi.com/softw are . sample programs for the fpga are available on-line as well. these can be found at www .latticesemi.com/boards . select fpga/fpsc boards -> latticemico32/dsp development board and click on the design files link. for further information please consult the latticeecp/ec family data sheet. parallel flash two parallel mx29lv128mbti-90q flash components from macronics are provided on the board for program code and data. as with the sram, a 32-bit data bus is realized with these two devices. thus, flash can be accessed as a 8mx32 memory. the 23-bit address bus, the data bus and the control signals are connected directly to the fpga . spi flash the latticeecp33 fpga is an sram-based programmable device, and is therefore volatile. in order for it to be automatically con?ured upon power-up, a non-volatile 8 mbit spi flash device is provided. the spi flash can be programmed with con?uration bitstream data. the spi flash can be con?ured either through the ispdown- load connector or via the integrated usb con?uration interface. important note: the board must be un-powered when connecting, disconnecting, or reconnecting the ispdown- load cable. always connect the ispdownload cable's gnd pin (black wire), before connecting any other jtag pins. failure to follow these procedures can in result in damage to the latticeecp2 fpga device and render the board inoperable. to program the spi flash con?uration device, use the fpga loader function of the ispvm system software. the fpga loader programming scheme provides an in-system jtag programming method for con?uration devices. the fpga acts as a bridge between the jtag interface and the spi interface of the serial con?uration device. con?ure the spi flash as follows: 1. in the ispvm system software, choose edit -> add device to open the device information dialog box. machxo pin signal name machxo pin machxo pin signal name machxo pin a1 machxo io0 c1 a2 machxo io1 e2 a3 machxo io2 f3 b3 machxo io3 r6 a4 machxo io4 u3 c4 machxo io5 v3 a5 machxo io6 v2 c8 machxo clk b1
22 latticemico32/dsp development board lattice semiconductor user? guide 2. click select to open the select device dialog box. 3. from the device family drop-down list, select fpga loader . the fpga loader opens and displays a setup menu in the left pane and instructions in the right pane. 4. from the menu, select cpld or fpga device to display the device con?uration dialog. 5. click select to open the select device dialog box. select device family latticeecp , device lfecp33e , and package 484 fpbga from the drop-down lists. 6. click ok to return to the fpga loader. 7. click the browse button under fpga loader application speci? data file and press the default button to use the standard ip provided for spi con?uration. click close to return to the fpga loader. 8. select fast program from the menu to open the data ?e dialog, and then select the con?uration data 1 with which you want the fpga to be programmed. 9. under con?uration data setup , browse to select the programming ?e you wish to load into the spi flash. this is the ?e that will ultimately be downloaded to the lfecp33e device. 10. select flash device from the menu to open the flash con?uration dialog. 11. under flash device, click select . select spi serial flash from the drop-down menu and select spi-m25p80 , stmicro and 8-pin soic . click ok to return to the fpga loader. 12. if desired, select hardware setup to display general information about the con?uration process. 13. click ok to exit the fpga loader, add the devices and return to the ispvm system software window. 14. click go . the ispvm system software programs the spi flash via the fpga. 15. disconnect and then reconnect the power supply. the fpga will take about three seconds to be programmed by the spi flash. power supply power is supplied via a 2.1 mm dc power jack in the top left corner of the board. the board is protected against reversed power supply. the input supply is 5v dc. a two-phase synchronous step-down switching regulator generates the 3.3v (1a max.) i/o voltage and the 1.2v (2a max.) core voltage. note: if you use a power supply other than the one included in the shipment, make sure it supplies regulated 5v. reset chip after power-up, a power surveillance chip (u0601) waits until the 5v supply and the 3.3v i/o voltage are stable. then, after 200 ms, it drives the signal hpe reset# (pin b3 of the fpga) high. if you press the reset button, the supervisory circuit will generate a low on the hpe reset# signal. the surveillance chip has an i 2 c serial 2 kbit cmos eeprom. the four most signi?ant bits of the 8-bit slave address are programmable; the default being 1010. detailed information on the reset circuit and the i 2 c interface can be found in the data sheet of the catalyst semiconductor cat1026. troubleshooting if your board is not working properly, please follow these steps for diagnosis. 1. usually a ?e with the ending .bit.
23 latticemico32/dsp development board lattice semiconductor user? guide 1. check the 3.3v and 2.5v leds to ensure that the power supply is working correctly. 2. make sure that the init led is lit. 3. load test program 1 1 . 4. make sure the fpga has been con?ured properly (done led must be lit). 5. start test program 1 (for a detailed description see the program 1 - peripheral test section of this document). circuit diagrams for the localization of errors can be found in the appendix. electrical speci?ations power requirement: regulated 5v dc input current: 2000 ma mechanical speci?ations dimensions: 160 mm [l] x 160 mm [w] x 31 mm [h] net weight: 160 g temperature range: 0 to 50 o c fpga pin information 1. if the content of the serial con?uration flash has not been overwritten since the time the board was shipped, you can altern atively unplug the power supply and then plug it in again. table 25. pin table pin name signal name appliance f21 hs dat2- high-speed lvds connector e22 hs dat2+ high-speed lvds connector f11 bb2v5 io0 fpga prototyping area f12 bb2v5 io1 fpga prototyping area f13 bb2v5 io2 fpga prototyping area g13 bb2v5 io3 fpga prototyping area f14 bb2v5 io4 fpga prototyping area g14 bb2v5 io5 fpga prototyping area f15 bb2v5 io6 fpga prototyping area f16 bb2v5 io7 fpga prototyping area f17 hs dat4+ high-speed lvds connector g17 hs dat4- high-speed lvds connector ab11 bb3v3 clk0- fpga prototyping area ab10 bb3v3 clk0+ fpga prototyping area ab13 bb3v3 io0 fpga prototyping area ab12 bb3v3 io1 fpga prototyping area t9 bb3v3 io10 fpga prototyping area u8 bb3v3 io11 fpga prototyping area aa12 bb3v3 io2 fpga prototyping area y12 bb3v3 io3 fpga prototyping area w12 bb3v3 io4 fpga prototyping area v12 bb3v3 io5 fpga prototyping area v11 bb3v3 io6 fpga prototyping area
24 latticemico32/dsp development board lattice semiconductor user? guide u10 bb3v3 io7 fpga prototyping area t10 bb3v3 io8 fpga prototyping area u9 bb3v3 io9 fpga prototyping area v20 cardsel# fpga prototyping area t20 cclk con?uration y21 cclk con?uration u18 cfg0 con?uration u19 cfg1 con?uration t19 cfg2 con?uration a10 clk fpga clock w1 codec bclk audio codec w4 codec cs# audio codec w2 codec din audio codec w3 codec dout audio codec aa1 codec lrcin audio codec y2 codec lrcout audio codec y3 codec mclk audio codec v4 codec mode audio codec y1 codec sclk audio codec aa2 codec sdin audio codec v21 csspin con?uration u7 dac dig dac d16 ddr a0 ddr ram c16 ddr a1 ddr ram e16 ddr a10 ddr ram c13 ddr a11 ddr ram b13 ddr a12 ddr ram c17 ddr a13 ddr ram e15 ddr a2 ddr ram d15 ddr a3 ddr ram c15 ddr a4 ddr ram e14 ddr a5 ddr ram d14 ddr a6 ddr ram c14 ddr a7 ddr ram e13 ddr a8 ddr ram d13 ddr a9 ddr ram e17 ddr ba0 ddr ram d17 ddr ba1 ddr ram a19 ddr cas# ddr ram a12 ddr ck0- ddr ram b12 ddr ck0+ ddr ram b19 ddr ck1- ddr ram a20 ddr ck1+ ddr ram a13 ddr cke0 ddr ram table 25. pin table (continued) pin name signal name appliance
25 latticemico32/dsp development board lattice semiconductor user? guide c12 ddr cke1 ddr ram b15 ddr dm0 ddr ram c20 ddr dm1 ddr ram h19 ddr dm2 ddr ram k20 ddr dm3 ddr ram a14 ddr dq0 ddr ram b14 ddr dq1 ddr ram c21 ddr dq10 ddr ram c22 ddr dq11 ddr ram e20 ddr dq12 ddr ram e18 ddr dq13 ddr ram f19 ddr dq14 ddr ram f18 ddr dq15 ddr ram d21 ddr dq16 ddr ram f20 ddr dq17 ddr ram g21 ddr dq18 ddr ram g20 ddr dq19 ddr ram a15 ddr dq2 ddr ram h20 ddr dq20 ddr ram j19 ddr dq21 ddr ram j18 ddr dq22 ddr ram h17 ddr dq23 ddr ram f22 ddr dq24 ddr ram g22 ddr dq25 ddr ram h22 ddr dq26 ddr ram h21 ddr dq27 ddr ram k19 ddr dq28 ddr ram k18 ddr dq29 ddr ram b16 ddr dq3 ddr ram l18 ddr dq30 ddr ram l19 ddr dq31 ddr ram a17 ddr dq4 ddr ram b17 ddr dq5 ddr ram a18 ddr dq6 ddr ram b18 ddr dq7 ddr ram b22 ddr dq8 ddr ram b21 ddr dq9 ddr ram a16 ddr dqs0 ddr ram d20 ddr dqs1 ddr ram h18 ddr dqs2 ddr ram j20 ddr dqs3 ddr ram c18 ddr ras# ddr ram c19 ddr s0# ddr ram b20 ddr s1# ddr ram table 25. pin table (continued) pin name signal name appliance
26 latticemico32/dsp development board lattice semiconductor user? guide d12 ddr vref ddr ram e19 ddr vref ddr ram d18 ddr we# ddr ram w22 dout con?uration r2 dsw0 dip switch r3 dsw1 dip switch r4 dsw2 dip switch r5 dsw3 dip switch t5 ec tck con?uration u5 ec tdi con?uration u1 ec tdo con?uration t4 ec tms con?uration k2 eth col ethernet k3 eth crs ethernet k5 eth mdc ethernet f1 eth mdintr# ethernet k4 eth mdio ethernet k1 eth rxclk ethernet g1 eth rxd0 ethernet g2 eth rxd1 ethernet g3 eth rxd2 ethernet f2 eth rxd3 ethernet j4 eth rxdv ethernet j5 eth rxer ethernet j1 eth txclk ethernet h1 eth txd0 ethernet h2 eth txd1 ethernet h3 eth txd2 ethernet h4 eth txd3 ethernet j3 eth txen ethernet j2 eth txer ethernet u20 expcon clkin expansion connector y22 expcon clkout expansion connector k22 expcon io0 expansion connector k21 expcon io1 expansion connector n22 expcon io10 expansion connector n21 expcon io11 expansion connector n20 expcon io12 expansion connector n19 expcon io13 expansion connector n18 expcon io14 expansion connector p22 expcon io15 expansion connector p21 expcon io16 expansion connector p20 expcon io17 expansion connector p18 expcon io18 expansion connector table 25. pin table (continued) pin name signal name appliance
27 latticemico32/dsp development board lattice semiconductor user? guide p19 expcon io19 expansion connector l22 expcon io2 expansion connector r22 expcon io20 expansion connector r21 expcon io21 expansion connector r19 expcon io22 expansion connector r18 expcon io23 expansion connector r17 expcon io24 expansion connector t22 expcon io25 expansion connector t18 expcon io26 expansion connector u22 expcon io27 expansion connector v19 expcon io28 expansion connector w21 expcon io29 expansion connector l21 expcon io3 expansion connector w20 expcon io30 expansion connector w19 expcon io31 expansion connector y20 expcon io32 expansion connector aa22 expcon io33 expansion connector aa21 expcon io34 expansion connector ab21 expcon io35 expansion connector t17 expcon io36 expansion connector t14 expcon io37 expansion connector t13 expcon io38 expansion connector u14 expcon io39 expansion connector l20 expcon io4 expansion connector u13 expcon io40 expansion connector u12 expcon io41 expansion connector u11 expcon io42 expansion connector v14 expcon io43 expansion connector v13 expcon io44 expansion connector w13 expcon io45 expansion connector m22 expcon io5 expansion connector m21 expcon io6 expansion connector m20 expcon io7 expansion connector m19 expcon io8 expansion connector m18 expcon io9 expansion connector aa5 flash byte# flash/sram y5 flash ce# flash/sram y6 flash reset# flash/sram w6 flash ry/by# a flash/sram w5 flash ry/by# b flash/sram ab5 flash wp#/acc flash/sram h6 hpe reset# reset b3 hpe resout# reset g19 hs dat1- high-speed lvds connector table 25. pin table (continued) pin name signal name appliance
28 latticemico32/dsp development board lattice semiconductor user? guide g18 hs dat1+ high-speed lvds connector j22 hs dat3- high-speed lvds connector j21 hs dat3+ high-speed lvds connector e21 hs dat0- high-speed lvds connector d22 hs dat0+ high-speed lvds connector l4 i2c scl1 i 2 c l5 i2c sda1 i 2 c r20 jtag done con?uration t21 jtag init con?uration p5 lcd enable lcd p3 lcd regsel lcd p4 lcd rw lcd e3 led0# led e4 led1# led e5 led2# led f4 led3# led f5 led4# led g4 led5# led g5 led6# led h5 led7# led b1 machxo clk0 con?uration c1 machxo io0 con?uration e2 machxo io1 con?uration f3 machxo io2 con?uration r6 machxo io3 con?uration u3 machxo io4 con?uration v3 machxo io5 con?uration v2 machxo io6 con?uration v1 clk fpga clock ab20 memory a0 flash/sram aa20 memory a1 flash/sram aa17 memory a10 flash/sram y17 memory a11 flash/sram w17 memory a12 flash/sram v17 memory a13 flash/sram u17 memory a14 flash/sram ab16 memory a15 flash/sram aa16 memory a16 flash/sram y16 memory a17 flash/sram w16 memory a18 flash/sram v16 memory a19 flash/sram ab19 memory a2 flash/sram u16 memory a20 flash/sram ab15 memory a21 flash/sram table 25. pin table (continued) pin name signal name appliance
29 latticemico32/dsp development board lattice semiconductor user? guide aa15 memory a22 flash/sram aa19 memory a3 flash/sram y19 memory a4 flash/sram ab18 memory a5 flash/sram aa18 memory a6 flash/sram y18 memory a7 flash/sram w18 memory a8 flash/sram ab17 memory a9 flash/sram y15 memory dq0 flash/sram w15 memory dq1 flash/sram aa11 memory dq10 flash/sram y11 memory dq11 flash/sram w11 memory dq12 flash/sram aa10 memory dq13 flash/sram y10 memory dq14 flash/sram w10 memory dq15 flash/sram v10 memory dq16 flash/sram ab9 memory dq17 flash/sram aa9 memory dq18 flash/sram y9 memory dq19 flash/sram v15 memory dq2 flash/sram w9 memory dq20 flash/sram v9 memory dq21 flash/sram ab8 memory dq22 flash/sram aa8 memory dq23 flash/sram y8 memory dq24 flash/sram w8 memory dq25 flash/sram v8 memory dq26 flash/sram ab7 memory dq27 flash/sram aa7 memory dq28 flash/sram y7 memory dq29 flash/sram u15 memory dq3 flash/sram w7 memory dq30 flash/sram v7 memory dq31 flash/sram ab14 memory dq4 flash/sram aa14 memory dq5 flash/sram y14 memory dq6 flash/sram w14 memory dq7 flash/sram aa13 memory dq8 flash/sram y13 memory dq9 flash/sram aa6 memory oe# flash/sram ab6 memory we# flash/sram v18 program# con?uration m1 rs cts lvttl rs232 table 25. pin table (continued) pin name signal name appliance
30 latticemico32/dsp development board lattice semiconductor user? guide l2 rs rts lvttl rs233 m2 rs rxd lvttl rs234 l1 rs txd lvttl rs235 m3 seg a# lcd, 7-segment display m4 seg b# lcd, 7-segment display m5 seg c# lcd, 7-segment display p1 seg ca0# lcd, 7-segment display p2 seg ca1# lcd, 7-segment display n1 seg d# lcd, 7-segment display n5 seg dp# lcd, 7-segment display n2 seg e# lcd, 7-segment display n3 seg f# lcd, 7-segment display n4 seg g# lcd, 7-segment display u21 sispi con?uration v22 spido con?uration ab4 sram be0# flash/sram aa4 sram be1# flash/sram ab3 sram be2# flash/sram aa3 sram be3# flash/sram y4 sram ce# flash/sram u4 tst col0 key matrix u6 tst col1 key matrix v5 tst col2 key matrix t1 tst row0 key matrix t2 tst row1 key matrix t3 tst row2 key matrix r1 tst row3 key matrix v6 tst step key matrix e6 usb cts usb b7 usb gpio0 usb c7 usb gpio1 usb f8 usb gpio10 usb a9 usb gpio11 usb b9 usb gpio12 usb c9 usb gpio13 usb d9 usb gpio14 usb e9 usb gpio15 usb f9 usb gpio16 usb g9 usb gpio17 usb b10 usb gpio18 usb c10 usb gpio19 usb d7 usb gpio2 usb d10 usb gpio20 usb e10 usb gpio21 usb table 25. pin table (continued) pin name signal name appliance
31 latticemico32/dsp development board lattice semiconductor user? guide f10 usb gpio22 usb g10 usb gpio23 usb b11 usb gpio24 usb c11 usb gpio25 usb d11 usb gpio26 usb e11 usb gpio27 usb e12 usb gpio28 usb e7 usb gpio3 usb f7 usb gpio4 usb a8 usb gpio5 usb b8 usb gpio6 usb c8 usb gpio7 usb d8 usb gpio8 usb e8 usb gpio9 usb c4 usb miso usb d3 usb mosi usb e1 usb oc0# usb d1 usb oc1# usb d2 usb oc2# usb b2 usb pwen0 usb c2 usb pwen1 usb c3 usb pwen2 usb d6 usb rts usb d5 usb rxd usb c6 usb sck usb c5 usb ssi# usb d4 usb txd usb a5 vga bl0 vga b6 vga bl1 vga a4 vga gr0 vga b5 vga gr1 vga a7 vga hsync vga a3 vga rd0 vga b4 vga rd1 vga a6 vga vsync vga table 25. pin table (continued) pin name signal name appliance
32 latticemico32/dsp development board lattice semiconductor user? guide figure 11. latticeecp33 bga pinout 12345678910111213141516171819202122 a gnd nc vga_ rd0 vga_ gr0 vga_ bl0 vga_ vsync vga_ hsync usb_ gpio5 usb_ gpio11 pclk t0_0 clkfpg pclk c0_0 ddr ck0- ddr cke0 ddr dq0 ddr dq2 tdqs46 ddr dqs0 ddr dq4 ddr dq6 ddr cas# ddr ck1+ nc gnd a b plltin machxo _clk0 usb_pwen 0 hpe_reso ut# vga_ rd1 vga_ gr1 vga_ bl1 usb_ gpio0 usb_ gpio6 usb_gpio 12 usb_gpio 18 usb_ gpio24 ddr ck0+ ddr a12 ddr dq1 ddr dm0 ddr dq3 ddr dq5 ddr dq7 ddr ck1- ddr s1# ddr dq9 ddr dq8 b c pllcin machxo _io0 usb_pwen 1 usb_pwen 2 usb_ d8/ msio usb_ d9 nssi usb_ d10/ sck usb_ gpio1 usb_ gpio7 usb_gpio 13 usb_ gpio19 usb_ gpio25 ddr cke1 ddr a11 ddr a7 ddr a4 tdqs54 ddr a1 ddr a13 ddr ras# ddr s0# ddr dm1 ddr dq10 plltfb ddr dq11 c d usb_ oc1# usb_ oc2# usb_ d11/ mosi usb_ d12/ txd usb_ d13/ rxd usb_ d14/ rts usb_ gpio2 usb_ gpio8 usb_gpio 14 usb_ gpio20 usb_ gpio26 vref11 ddr vref ddr a9 ddr a6 ddr a3 ddr a0 ddr ba1 ddr we# vref 22 ddr vref rdqs14 ddr dqs1 pllcfb ddr dq16 hscon_ dat0+ d e usb_ oc0# pllcfb machxo _io1 led0# led1# led2# usb_ d15/ cts usb_ gpio3 usb_ gpio9 usb_gpio 15 usb_ gpio21 usb_ gpio27 usb_ gpio28 ddr a8 ddr a5 ddr a2 ddr a10 ddr ba0 ddr dq13 vref12 ddr dq12 hscon_ dat0- hscon_ dat2+ e f ethernet mdintr# ethernet rxd3 plltfb machxo_i o2 led3# led4# usb_ gpio4 usb_ gpio10 usb_gpio 16 usb_ gpio22 bb2v5 _io0 vref21 bb2v5 _io1 bb2v5 _io2 bb2v5 _io4 bb2v5 _io6 bb2v5 _io7 hscon_ dat4+ ddr dq15 ddr dq14 ddr dq17 hscon_ dat2- ddr dq24 f g ethernet rxd0 ethernet rxd1 ethernet rxd2 led5# led6# vcc 3.3v vcc 3.3v usb_gpio 17 usb_ gpio23 vcc 3.3v vcc 3.3v tdqs38 bb2v5 _io3 bb2v5 _io5 vcc 3.3v vcc 3.3v hscon_ dat4- plltin hscon_ dat1+ pllcin hscon_ dat1- ddr dq19 ddr dq18 ddr dq25 g h ethernet txd0 ethernet txd1 ethernet txd2 ethernet txd3 led7# hpe_ reset# vcc 3.3v gnd vcc 3.3v vcc 3.3v vcc 3.3v vcc 3.3v vcc 3.3v vcc 3.3v gnd vcc 3.3v ddr dq23 rdqs23 ddr dqs2 ddr dm2 ddr dq20 ddr dq27 ddr dq26 h j pclk t70 eth txclk ethernet txer ethernet txen ethernet rxdv ethernet rxer vcc pll vcc 1.2v vcc 3.3v gnd gnd gnd gnd gnd gnd vcc 3.3v vcc 1.2v vcc pll ddr dq22 ddr dq21 rdqs31 ddr dqs3 pclkt2 hscon_ dat3+ pclkc2 hscon_ dat3- j k pclk c70eth rxclk ethernet col ethernet crs ethernet mdio ethernetmd c vcc 1.2v vcc 1.2v vcc 3.3v gnd gnd gnd gnd gnd gnd vcc 3.3v vcc 1.2v vcc 1.2v ddr dq29 ddr dq28 ddr dm3 expcon_io 1 expcon_io 0 k l rs_txd0_ ttl rs_rts0_ ttl xres i2c_scl1 i2c_sda1 vcc 1.2v vcc 3.3v vcc 3.3v gnd gnd gnd gnd gnd gnd vcc 3.3v vcc 3.3v vcc 1.2v ddr dq30 ddr dq31 rdqs40 expcon_io 4 expcon_io 3 expcon_io 2 l m rs_cts0_ ttl rs_rxd0_ ttl seg _a# seg _b# seg _c# vcc 1.2v vcc 3.3v vcc 3.3v gnd gnd gnd gnd gnd gnd vcc 3.3v vcc 3.3v vcc 1.2v expcon_io 9 expcon_io 8 expcon_io 7 expcon_io 6 expcon_io 5 m n seg _d# seg _e# seg _f# seg _g# seg _dp# vcc 1.2v vcc 1.2v vcc 3.3v gnd gnd gnd gnd gnd gnd vcc 3.3v vcc 1.2v vcc 1.2v expcon_io 14 expcon_io 13 expcon_io 12 expcon_io 11 expcon_io 10 n p seg _ca0# seg _ca1# lcd_ regsel lcd_ rw lcd_ enable vcc pll vcc 1.2v vcc 3.3v gnd gnd gnd gnd gnd gnd vcc 3.3v vcc 1.2v vcc pll expcon_io 19 expcon_io 18 expcon_io 17 expcon_io 16 expcon_io 15 p r tst_ row3 dsw0 dsw1 dsw2 dsw3 machxo_io 3 vcc 3.3v gnd vcc 3.3v vcc 3.3v vcc 3.3v vcc 3.3v vcc 3.3v vcc 3.3v gnd vcc 3.3v expcon_io 24 rdqs48 expcon_io 23 expcon_io 22 conf done expcon_io 21 expcon_io 20 r t tst_ row0 tst_ row1 tst_ row2 jtag tms jtag tck vcc 3.3v vcc 3.3v bb3v3 _io10 bb3v3 _io8 vcc 3.3v vcc 3.3v bdqs38 expcon_io 38 expcon_io 37 vcc 3.3v vcc 3.3v expcon_io 36 expcon_io 26 conf cfg2 flash cclk conf initn expcon_io 25 t u jtag tdo vcc 3.3v plltfb machxo_i o4 tst_ col0 jtag tdi tst_ col1 dacdig bb3v3 _io11 bb3v3 _io9 bb3v3 _io7 cs1n expcon_io 42 conf expcon_io 41 confd0 expcon_io 40 confd4 expcon_io 39 mem dq3 mem a20 mem a14 conf cfg0 conf cfg1 plltin expcon_cl kin flash sispi expcon_io 27 u v plltin clk_fpga pllcin machxo _io6 pllcfb machxo _io5 codec_m ode tst_ col2 tst_ step mem dq31 mem dq26 bdqs22 mem dq21 mem dq16 vref25 bb3v3 _io6 vref15 bb3v3 _io5 confd3 expcon_io 44 confd5 expcon_io 43 mem dq2 mem a19 mem a13 conf program n expcon_io 28 pllcin cardsel# flash csspin flash spido v w codec_bc lk codec_di n codec_d out codec_cs # flash ry/by# b flash ry/by# a mem dq30 mem dq25 mem dq20 mem dq15 mem dq12 vref14 bb3v3 _io4 vref24 expcon_io 45 mem dq7 mem dq1 mem a18 mem a12 mem a8 expcon_io 31 vref23 expcon_io 30 pllcfb expcon_io 29 conf dout cson w y codec_sc lk codec_lr cout codec_m clk sram ce# flash ce# bdqs14 flash reset# mem dq29 mem dq24 mem dq19 mem dq14 mem dq11 wrien bb3v3 _io3 mem dq9 mem dq6 mem dq0 bdqs54 mem a17 mem a11 mem a7 mem a4 vref13 expcon_io 32 flash cclk plltfb expcon_cl kout y aa codec_lr cin codec_sd in sram be3# sram be1# flash byte# mem oe# mem dq28 mem dq23 mem dq18 bdqs30 mem dq13 mem dq10 confd2 bb3v3 _io2 mem dq8 mem dq5 mem a22 mem a16 mem a10 mem a6 mem a3 mem a1 expcon_io 34 rdqs57 expcon_io 33 a a ab gnd nc sram be2# sram be0# flash wp#/ acc mem we# mem dq27 mem dq22 mem dq17 pclkt5 bb3v3 _clk0+ pclkc5 bb 3v3 _clk0- confd1 bb3v3 _io1 confd6 bb3v3 _io0 mem dq4 mem a21 bdqs46 mem a15 mem a9 mem a5 mem a2 mem a0 expcon_io 35 gnd a b 12345678910111213141516171819202122 bank1 bank2 bank3 bank4 bank5 bank6 bank7 bank0 gnd vcc 2.5 v 2.5 v 3,3 v 3.3 v 3.3 v 3.3 v 3.3 v 3.3 v
33 latticemico32/dsp development board lattice semiconductor user? guide ordering information technical support assistance hotline: 1-800-lattice (north america) +1-503-268-8001 (outside north america) e-mail: techsupport@latticesemi.com internet: www .latticesemi.com revision history ?2007 lattice semiconductor corp. all lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www .latticesemi.com/legal . all other brand or product names are trademarks or registered trademarks of their respective holders. the speci?ations and information herein are subject to change without notice. portions copyright 2005 - 2006 gleichmann and company electronics gmbh. description ordering part number china rohs environment-friendly use period (efup) latticemico32/dsp development board lfecp33e-d-ev isplever base with latticemico32/dsp development kit LS-ECP33-BASE-PC-N date version change summary july 2006 01.0 initial release. march 2007 01.1 added ordering information section. april 2007 01.2 ordering information (efup) updated. april 2007 01.3 added important information for proper connection of ispdownload (programming) cables. october 2007 01.4 added note to ddr sodimm socket for ddr sdram modules text section. updated fpga pin column in the serial interface x1c pin de?itions table. 10
34 latticemico32/dsp development board lattice semiconductor user? guide appendix a. schematics figure 12. 5 5 4 4 3 3 2 2 1 1 d d c c b b a a seg_ca0# seg_a# seg_b# seg_c# seg_d# seg_e# seg_f# seg_dp# dsw0 dsw1 dsw2 dsw3 seg_ca1# seg_g# tst_step tst_col0 tst_col2 tst_col1 led7# led0# led1# led2# led3# led5# led6# tst_row0 tst_row3 tst_row2 tst_row1 lcd_regsel lcd_rw lcd_enable rs_cts_lvttl rs_rxd_lvttl rs_txd_lvttl rs_rts_lvttl usb_gpio[28:0] usb_pwen0 usb_oc0# usb_pwen1 usb_oc1# usb_pwen2 usb_oc2# cardsel# codec_sclk codec_din codec_cs# codec_bclk codec_lrcin codec_dout codec_mclk codec_lrcout codec_sdin vga_rd0 vga_rd1 vga_gr0 vga_bl0 vga_gr1 vga_hsync vga_bl1 vga_vsync led4# eth_txer eth_txd3 eth_txd1 eth_txd0 eth_txen eth_txclk eth_rxer eth_rxd3 eth_rxd2 eth_rxd0 eth_rxclk eth_rxdv eth_crs eth_col eth_rxd1 eth_txd2 eth_mdc eth_mdio eth_mdintr# hpe_resout# clk_fpga expcon_clkin expcon_clkout i2c_scl1 i2c_sda1 dac_dig dac_analog flash_ce# sram_ce# memory_oe# memory_we# flash_wp#/acc memory_a[22:0] memory_dq[31:0] flash_byte# flash_ry/by#_a flash_ry/by#_b sram_be0# sram_be1# sram_be2# sram_be3# flash_reset# hpe_reset# expcon_io[45:0] usb_miso usb_ssi# usb_sck usb_mosi usb_txd ddr_cke0 ddr_ba0 ddr_we# ddr_ras# ddr_cas# ddr_s0# ddr_dq[31:0] ddr_a[13:0] ddr_ck0+ ddr_ck0- ddr_dqs[3:0] ddr_dm[3:0] ddr_ck1+ codec_mode usb_rxd usb_rts usb_cts machxo_io[6:0] machxo_clk0 ddr_cke1 ddr_vref ddr_s1# ddr_ba1 ddr_ck1- hscon_dat1+ hscon_dat1- hscon_dat2+ hscon_dat2- hscon_dat0+ hscon_dat0- hscon_dat3+ hscon_dat3- hscon_dat0- hscon_dat0+ hscon_dat1+ hscon_dat1- hs_dat1- hs_dat1+ hs_dat0+ hs_dat0- hscon_dat3- hscon_dat2- hscon_dat2+ hscon_dat3+ hs_dat2+ hs_dat2- clk_fpga vga_rd0 vga_rd1 vga_gr0 vga_bl0 vga_gr1 vga_hsync vga_bl1 vga_vsync usb_gpio0 usb_gpio1 usb_gpio2 usb_gpio3 usb_gpio4 usb_gpio5 usb_gpio6 usb_gpio7 usb_gpio8 usb_gpio9 usb_gpio10 usb_gpio11 usb_gpio12 usb_gpio13 usb_gpio14 usb_gpio15 usb_gpio16 usb_gpio17 usb_gpio18 usb_gpio19 usb_gpio20 usb_gpio21 usb_gpio22 usb_gpio23 usb_gpio24 usb_gpio25 usb_gpio26 usb_gpio27 usb_gpio28 memory_dq5 memory_dq6 memory_dq3 memory_dq1 memory_dq2 memory_dq0 memory_dq7 memory_dq4 memory_dq9 memory_dq8 memory_a9 memory_a11 memory_a10 memory_a13 memory_a15 memory_a14 memory_a12 memory_a17 memory_a19 memory_a18 memory_a16 memory_a21 memory_a22 memory_a20 memory_a5 memory_a7 memory_a6 memory_a4 memory_a1 memory_a3 memory_a2 memory_a0 memory_a8 memory_dq11 memory_dq10 memory_dq15 memory_dq12 memory_dq17 memory_dq19 memory_dq18 memory_dq16 memory_dq21 memory_dq23 memory_dq22 memory_dq20 memory_dq24 memory_dq26 memory_dq28 memory_dq27 memory_dq25 memory_dq30 memory_dq31 memory_dq29 memory_dq13 memory_dq14 sram_ce# sram_be0# sram_be1# memory_oe# memory_we# flash_ce# flash_wp#/acc flash_byte# flash_ry/by#_a flash_ry/by#_b flash_reset# sram_be3# sram_be2# i2c_sda1 i2c_scl1 rs_cts_lvttl rs_rxd_lvttl rs_rts_lvttl rs_txd_lvttl tst_row0 tst_row1 tst_row2 tst_row3 tst_step dsw0 dsw1 dsw2 dsw3 led0# led1# led2# led3# led4# led5# led6# led7# seg_c# seg_d# seg_g# seg_dp# seg_ca0# seg_ca1# lcd_rw lcd_regsel lcd_enable tst_col0 seg_a# seg_b# seg_e# seg_f# tst_col2 machxo_io5 machxo_io3 machxo_io4 machxo_io6 clk_fpga hpe_reset# machxo_clk0 machxo_io0 machxo_io1 machxo_io2 eth_txer eth_rxdv eth_crs eth_col eth_mdc eth_mdio eth_mdintr# eth_txclk eth_rxclk eth_txd3 eth_txd1 eth_txen eth_txd2 eth_rxer eth_rxd2 eth_rxd0 eth_rxd1 eth_rxd3 eth_txd0 usb_mosi usb_txd usb_oc0# usb_pwen0 usb_pwen1 usb_pwen2 usb_oc1# usb_oc2# ddr_dqs3 ddr_dm3 ddr_a9 ddr_a11 ddr_a12 ddr_a5 ddr_a6 ddr_a7 ddr_a8 ddr_a1 ddr_a2 ddr_a3 ddr_a4 ddr_a0 ddr_a13 ddr_dq28 hs_dat3+ ddr_a10 ddr_dq24 ddr_dq25 ddr_dq26 ddr_dq27 ddr_dq29 ddr_dq30 ddr_dq31 ddr_cke1 ddr_cas# ddr_ras# ddr_vref ddr_ba0 ddr_ba1 ddr_we# ddr_s0# ddr_s1# ddr_dq0 ddr_dq6 ddr_dq5 ddr_dm0 ddr_dqs0 ddr_dq4 ddr_dqs2 ddr_dm2 ddr_dq16 ddr_dq17 ddr_dq18 ddr_dq19 ddr_dq20 ddr_dq21 ddr_dq22 ddr_dq23 hs_dat1+ hs_dat1- ddr_ck0+ ddr_ck0- hs_dat0+ hs_dat0- ddr_ck1+ ddr_ck1- ddr_vref ddr_dqs1 ddr_dm1 ddr_dq7 ddr_dq1 ddr_dq3 ddr_dq2 ddr_dq8 ddr_dq9 ddr_dq10 ddr_dq11 ddr_dq12 ddr_dq13 ddr_dq14 ddr_dq15 ddr_cke0 bb3v3_clk0- bb3v3_io[11:0] bb3v3_clk0+ bb3v3_clk0- bb3v3_clk0+ bb3v3_io4 bb3v3_io5 bb3v3_io6 bb3v3_io7 bb3v3_io8 bb3v3_io9 bb3v3_io10 bb3v3_io11 bb2v5_io0 bb2v5_io1 bb2v5_io2 bb2v5_io3 bb2v5_io4 bb2v5_io5 bb2v5_io7 hs_dat4+ hs_dat4- bb2v5_io6 expcon_io1 expcon_io3 expcon_io2 expcon_io0 expcon_io7 expcon_io14 expcon_io4 expcon_io8 expcon_io9 expcon_io5 expcon_io23 expcon_io24 expcon_io22 expcon_io27 expcon_io26 expcon_io25 expcon_io30 expcon_io29 expcon_io28 expcon_io32 expcon_io31 expcon_io35 expcon_io33 expcon_io34 expcon_io10 expcon_io13 expcon_io12 expcon_io6 expcon_io15 expcon_io11 expcon_io18 expcon_io16 expcon_io19 expcon_io17 expcon_io20 expcon_clkin expcon_clkout expcon_io21 cardsel# expcon_io36 expcon_io37 expcon_io38 expcon_io45 dac_dig tst_col1 codec_din codec_mclk codec_dout codec_cs# codec_sclk codec_lrcin codec_bclk codec_sdin codec_lrcout codec_mode hpe_resout# usb_miso usb_ssi# usb_sck usb_rxd usb_rts usb_cts bb2v5_io[7:0] hs_dat3+ hs_dat2+ hs_dat2- hs_dat3- hs_dat3- hscon_dat4- hscon_dat4+ hs_dat4+ hs_dat4- hscon_dat4+ hscon_dat4- gnd gnd_dac gnd_dac gnd gnd gnd vcc2v5 gnd vcc1v2 vcc3v3 gnd gnd vcc2v5 vcc3v3 vcc2v5 vcc3v3 vcc3v3 vcc3v3 vcc3v3 vcc3v3 gnd vcc3v3 vcc1v2 gnd dsw0 5 dsw1 5 dsw2 5 dsw3 5 tst_row0 5 tst_row1 5 tst_row2 5 led0# 5 tst_row3 5 led2# 5 led1# 5 led3# 5 led5# 5 led4# 5 led6# 5 seg_ca0# 5 led7# 5 seg_b# 5 seg_ca1# 5 seg_c# 5 seg_e# 5 seg_f# 5 seg_g# 5 seg_a# 5 seg_dp# 5 tst_col0 5 seg_d# 5 tst_col1 5 tst_step 5 tst_col2 5 lcd_regsel 5 lcd_rw 5 lcd_enable 5 rs_cts_lvttl 7 rs_rxd_lvttl 7 rs_txd_lvttl 7 rs_rts_lvttl 7 usb_gpio[28:0] 7 usb_pwen0 7 usb_oc0# 7 usb_pwen1 7 usb_oc1# 7 usb_pwen2 7 usb_oc2# 7 cardsel# 9 codec_sclk 10 codec_din 10 codec_cs# 10 codec_bclk 10 codec_lrcin 10 codec_dout 10 codec_mclk 10 codec_lrcout 10 codec_sdin 10 vga_rd0 10 vga_rd1 10 vga_gr0 10 vga_gr1 10 vga_bl0 10 vga_hsync 10 vga_bl1 10 vga_vsync 10 eth_txer 8 eth_txd3 8 eth_txd2 8 eth_txd1 8 eth_txd0 8 eth_txen 8 eth_txclk 8 eth_rxer 8 eth_rxd3 8 eth_rxd2 8 eth_rxd1 8 eth_rxd0 8 eth_rxclk 8 eth_rxdv 8 eth_crs 8 eth_col 8 eth_mdintr# 8 eth_mdc 8 eth_mdio 8 hpe_resout# 6,7,8,9 clk_fpga 6 expcon_clkin 9 expcon_clkout 9 i2c_sda1 6 i2c_scl1 6 flash_ce# 4 sram_ce# 4 memory_oe# 4 memory_we# 4 flash_wp#/acc 4 memory_a[22:0] 4memory_dq[31:0] 4 flash_byte# 4 flash_ry/by#_a 4 flash_ry/by#_b 4 sram_be0# 4 sram_be1# 4 sram_be2# 4 sram_be3# 4 flash_reset# 4 hpe_reset# 3,6 expcon_io[45:0] 3,9 usb_miso 7 usb_ssi# 7 usb_sck 7 usb_mosi 7 usb_txd 7 ddr_cke0 4 ddr_ba0 4ddr_ba1 4 ddr_vref 4 ddr_we# 4 ddr_ras# 4 ddr_cas# 4 ddr_s0# 4 ddr_s1# 4 ddr_dq[31:0] 4 ddr_a[13:0] 4 ddr_ck0+ 4 ddr_ck0- 4 ddr_dqs[3:0] 4 ddr_dm[3:0] 4 ddr_ck1+ 4 codec_mode 10 usb_rxd 7 usb_rts 7 usb_cts 7 machxo_io[6:0] 3machxo_clk0 3 ddr_cke1 4 ddr_ck1- 4 hscon_dat1+ 9 hscon_dat1- 9 hscon_dat2+ 9 hscon_dat2- 9 hscon_dat0+ 9 hscon_dat0- 9 hscon_dat3+ 9 hscon_dat3- 9 bb3v3_clk0- 9 bb3v3_clk0+ 9 bb3v3_io[11:0] 3,9 bb2v5_io[7:0] 9 hscon_dat4+ 9 hscon_dat4- 9 : t e e h s : t c e j o r p authors: revision: created: last modified: ifw: of page a g p f _ 2 0 12 2 lattice lfec33 fpga offpage human interface rs232 usb ethernet expansion connectors and prototyping area audio codec vga clock / reset sternpunkt an x1 memory dac configuration lvds termination lvds lvds lvds lvds lvds lvds lvds lvds place the 0402-resistors of the lvds termination as close as possible to the fpga. lvds lvds lvds lvds lvds lvds lvds r0209 0r00 12 bank 2 bank 3 u0201b lfecp/ec33-484bga pr34b/pclkc2_0 j22 pr34a/pclkt2_0 j21 pr33b h22 pr33a h21 pr32b l19 pr32a l18 pr31b k20 pr30a k18 pr30b k19 pr31a/rdqs31 j20 pr29b g22 pr29a f22 pr28b f21 pr28a e22 pr27b e21 pr27a d22 pr26b g21 pr26a g20 pr25b j18 pr25a h19 pr24b j19 pr24a h20 pr23b h17 pr23a/rdqs23 h18 pr17b/ru_pllc_fb d21 pr17a/ru_pllt_fb c22 pr16b/ru_pllc_in g19 pr16a/ru_pllt_in g18 pr15b f20 pr15a f19 pr14b e20 pr14a/rdqs14 d20 pr13b c21 pr13a c20 pr12b f18 pr12a e18 pr11b b22 pr11a b21 pr2b/vref1_2 e19 pr2a/vref2_2 d19 vref1_3/pr68a y20 vref2_3/pr68b w20 pr59a ab21 pr59b aa21 pr58a v19 pr58b w19 rdqs57/pr57a aa22 rl_pllt_in/pr56a u20 rl_pllc_in/pr56b v20 rl_pllt_fb/pr55a y22 rl_pllc_fb/pr55b w21 pr49a r17 pr49b t18 rdqs48/pr48a r18 pr47b u22 pr46b r21 pr45b p20 pr44b p19 pr43b p21 pr42b n21 pr41b n19 pr40b m21 pr39b l21 pr38b m18 pr37b m22 pr36b k22 pr48b r19 pr47a t22 pr46a r22 pr45a n20 pr44a p18 pr43a p22 pr42a n22 pr41a n18 rdqs40/pr40a l20 pr39a m20 pr38a m19 pr37a l22 pr36a k21 r0213 nb_100r 12 100n c0224 100n c0218 100n c0212 r0211 0r00 12 100n c0234 100n c0230 r0204 nb_100r 12 nb_4p70 c0240 r0215 0r00 12 r0210 nb_100r 12 100n c0213 1n00 c0228 100n c0203 100n c0231 bank 0 bank 1 u0201a lfecp/ec33-484bga pt33b/pclkc0_0 a11 pt33a/pclkt0_0 a10 pt32b/vref1_0 e12 pt32a/vref2_0 e11 pt31b b11 pt31a c11 pt30b b9 pt30a/tdqs30 b10 pt29b a9 pt29a a8 pt28b d11 pt28a c10 pt27b a7 pt27a a6 pt26b b7 pt25a b6 pt25b a5 pt26a b8 pt24b g10 pt24a e10 pt23b f10 pt23a d10 pt22b g9 pt22a/tdqs22 e9 pt21b c9 pt21a c8 pt20b f9 pt20a d9 pt19b f8 pt19a d7 pt18b d8 pt18a c7 pt17b a4 pt17a b4 pt16b c4 pt16a c5 pt15b d6 pt15a b5 pt14b e6 pt14a/tdqs14 c6 pt13b a3 pt13a b3 pt12b f6 pt12a d5 pt11b f7 pt11a e8 pt10b g6 pt10a e7 pt57a f17 pt57b g17 pt56a c18 pt56b d18 pt55a b20 pt55b c19 tdqs54/pt54a c16 pt54b d17 pt53a a20 pt53b b19 pt52a c17 pt52b e17 pt51a e16 pt51b f16 pt50a d16 pt50b f15 pt49a a19 pt49b b18 pt48a a18 pt48b b17 pt47a a17 pt47b b16 tdqs46/pt46a a16 pt45b a15 pt44b g14 pt43b d15 pt42b c14 pt41b a13 pt40b e14 pt39b f14 pt38b e13 pt37b a12 pt36b f13 vref2_1/pt35b f12 pt34b f11 pt46b b15 pt45a a14 pt44a e15 pt43a c15 pt42a b14 pt41a b13 pt40a c13 pt39a d14 tdqs38/pt38a g13 pt37a b12 pt36a d13 vref1_1/pt35a d12 pt34a c12 r0217 0r00 12 100n c0235 100n c0227 power supply u0201f lfecp/ec33-484bga gnd r8 gnd r15 gnd p9 gnd p14 gnd p13 gnd p12 gnd p11 gnd p10 gnd n9 gnd n14 gnd n13 gnd n12 gnd n11 gnd n10 gnd m9 gnd m14 gnd m13 gnd m12 gnd m11 gnd m10 gnd l9 gnd l14 gnd l13 gnd l12 gnd l11 gnd l10 gnd k9 gnd k14 gnd k13 gnd k12 gnd k11 gnd k10 gnd j9 gnd j14 gnd j13 gnd j12 gnd j11 gnd j10 gnd h8 gnd h15 gnd ab22 gnd ab1 gnd a22 gnd a1 vcc j16 vcc j7 vcc k16 vcc k17 vcc k6 vcc k7 vcc l17 vcc l6 vcc m17 vcc m6 vcc n16 vcc n17 vcc n6 vcc n7 vcc p16 vcc p7 vccio0 g11 vccio0 h10 vccio0 h11 vccio0 h9 vccio1 g12 vccio1 h12 vccio1 h13 vccio1 h14 vccio2 j15 vccio2 k15 vccio2 l15 vccio2 l16 vccio3 m15 vccio3 m16 vccio3 n15 vccio3 p15 vccio4 r12 vccio4 r13 vccio4 r14 vccio4 t12 vccio5 r10 vccio5 r11 vccio5 r9 vccio5 t11 vccio6 m7 vccio6 m8 vccio6 n8 vccio6 p8 vccio7 j8 vccio7 k8 vccio7 l7 vccio7 l8 r0206 0r00 12 100n c0201 100n c0225 100n c0232 100n c0202 r0208 0r00 1 2 + c0220 4u70 1 2 r0216 nb_100r 12 100n c0214 100n c0215 + c0211 4u70 1 2 bank 4 bank 5 u0201c lfecp/ec33-484bga pb57b u17 pb57a t17 pb56b w18 pb56a y18 pb55b y19 pb54a/bdqs54 y16 pb54b w17 pb55a aa20 pb53b aa19 pb53a ab20 pb52b v17 pb52a y17 pb51b u16 pb51a v16 pb50b u15 pb50a w16 pb49b aa18 pb49a ab19 pb48b aa17 pb48a ab18 pb47b aa16 pb47a ab17 pb46b aa15 pb46a/bdqs46 ab16 pb45b ab15 pb45a ab14 pb44b t14 pb44a v15 pb43b w15 pb43a y15 pb42b y14 pb42a aa14 pb41a aa13 pb40a y13 pb39a w14 pb38a/bdqs38 t13 pb36a/vref2_4 w13 pb35a/vref1_4 w12 pb29a ab8 pb29b ab9 pb28a y10 pb28b w11 pb27a ab6 pb27b ab7 pb26a aa8 pb26b aa7 pb25a aa6 pb25b ab5 pb24a v10 pb24b t10 pb23a w10 pb23b u10 bdqs22/pb22a v9 pb21b y9 pb20b u9 pb19b u8 pb18b w8 pb17b ab4 pb16b y4 pb15b w6 pb14b v6 pb13b ab3 pb12b u6 pb11b u7 pb10b t6 pb22b t9 pb21a y8 pb20a w9 pb19a w7 pb18a y7 pb17a aa4 pb16a y5 pb15a aa5 bdqs14/pb14a y6 pb13a aa3 pb12a w5 pb11a v8 pb10a v7 bdqs30/pb30a aa10 pb30b aa9 pb31a y11 pb31b aa11 vref2_5/pb32a v11 vref1_5/pb32b v12 pclkt5_0/pb33a ab10 pclkc5_0/pb33b ab11 r0212 0r00 12 r0207 nb_100r 12 100n c0236 r0202 33k2 1 2 100n c0221 100n c0226 4p70 c0239 x1 hdr2 1 2 100n c0216 r0214 0r00 12 r0203 0r00 12 r0205 0r00 12 1n00 c0210 100n c0222 1n00 c0219 bank 6 bank 7 u0201d lfecp/ec33-484bga pl57b y2 pl57a/ldqs57 y1 pl56b w2 pl56a w1 pl55b v5 pl54a/ll_pllt_fb u3 pl54b/ll_pllc_fb v3 pl55a u4 pl53b/ll_pllc_in v2 pl53a/ll_pllt_in v1 pl49b t3 pl49a r3 pl48b t2 pl48a/ldqs48 t1 pl47b r4 pl47a r5 pl46b r2 pl46a r1 pl45b p4 pl45a p3 pl44b p5 pl44a r6 pl43b p2 pl43a p1 pl42b n2 pl42a n1 pl41b n4 pl41a n5 pl40b m3 pl40a/ldqs40 n3 pl39b m2 pl39a m1 pl38b m5 pl38a m4 pl37b l1 pl37a l2 pl36b l5 pl36a l4 pclkt7_0/pl34a j1 pclkc7_0/pl34b k1 pl33a k3 pl33b k2 pl32a k4 pl32b k5 ldqs31/pl31a j2 pl31b h1 pl30a j4 pl30b j3 pl29a h2 pl29b g1 pl28a h3 pl28b g2 pl27a e1 pl26b f1 pl25b h5 pl24b h4 pl23b h6 pl15b d2 pl14b g4 pl12b c2 pl11b f5 pl10b b2 vref1_7/pl2b e4 pl27b d1 pl26a f2 pl25a j5 pl24a g3 ldqs23/pl23a g5 lu_pllt_in/pl16a b1 pl15a e3 ldqs14/pl14a f4 pl12a d3 pl11a e5 pl10a c3 vref2_7/pl2a d4 lu_pllc_in/pl16b c1 lu_pllt_fb/pl17a f3 lu_pllc_fb/pl17b e2 pl58a aa1 pl58b aa2 pl59a w4 pl59b v4 pl68a/vref1_6 w3 pl68b/vref2_6 y3 100n c0208 r0201 0r00 1 2 100n c0217 + c0229 4u70 1 2
35 latticemico32/dsp development board lattice semiconductor user? guide figure 13. 5 5 4 4 3 3 2 2 1 1 d d c c b b a a vccpll ec_tdo jtag_done sispi csspin cfg2 cfg1 cfg0 jtag_init ec_tdi ec_tms spido cclk program# machxo_io[6:0] machxo_clk0 gp_adr8 usbcf_wake usbcf_p usbcf_m usbcf_i2c_sda usbcf_i2c_scl usb_clk_o gp_int0 gp_int1 gp_bkpt gp_ctl5 gp_ctl0 gp_ctl1 gp_ctl2 gp_ctl4 gp_ctl3 gp_sloe gp_wu2 gp_fifoadr0 gp_fifoadr1 gp_ifclk gp_pktend gp_slcs# gp_t0 gp_t1 gp_t2 gp_rdy0 gp_rdy1 gp_rdy2 gp_rdy3 gp_rdy4 gp_rdy5 gp_rxd0 gp_txd0 gp_rxd1 gp_txd1 gp_d0 gp_d1 gp_d2 gp_d3 gp_d4 gp_d5 gp_d6 gp_d7 gp_d8 gp_d9 gp_d10 gp_d11 gp_d12 gp_d13 gp_d14 gp_d15 gp_adr0 gp_adr1 gp_adr2 gp_adr3 gp_adr4 gp_adr5 gp_adr6 gp_adr7 jtag_tck jtag_tms jtag_tdi jtag_tdo jtag_prog jtag_trst jtag_done jtag_init dout bb3v3_io[11:0] aa3v3_io1 aa3v3_io21 aa3v3_io20 aa3v3_io19 aa3v3_io2 aa3v3_io3 aa3v3_io0 aa3v3_io18 ec_tck jtag_done cfg0 program# cfg1 cfg2 jtag_init aa3v3_io7 aa3v3_io8 aa3v3_io9 aa3v3_io10 aa3v3_io11 aa3v3_io12 aa3v3_io13 aa3v3_io14 aa3v3_io4 aa3v3_io17 aa3v3_io6 aa3v3_io15 aa3v3_io5 aa3v3_io16 jtag_tms gpio_tms i d t _ c e i d t _ o x h c a m i d t _ g a t jgpio_tdo o d t _ c e o d t _ o x h c a m o d t _ g a t jgpio_tdi k c t _ c e k c t _ o x h c a m k c t _ g a t jgpio_tck aa3v3_io1 aa3v3_io2 aa3v3_io3 aa3v3_io4 usb_sda machxo_io6 usb_scl aa3v3_io6 aa3v3_io7 aa3v3_io8 aa3v3_io9 aa3v3_io10 aa3v3_io11 aa3v3_io12 aa3v3_io13 aa3v3_io14 aa3v3_io0 machxo_io0 machxo_io1 machxo_io2 machxo_io3 machxo_io4 machxo_io5 gp_rxd0 gp_txd0 gp_rxd1 gp_txd1 gp_bkpt aa3v3_io15 aa3v3_io5 aa3v3_io16 aa3v3_io17 aa3v3_io18 gp_adr6 gp_adr7 gp_adr8 hpe_reset# gp_d0 gp_d1 gp_d2 gp_d3 gp_d4 gp_d5 gp_d6 gp_d7 gp_d8 gp_d9 gp_d10 gp_t1 gp_t2 gp_t0 gp_ctl3 gp_ctl2 gp_ctl1 gp_ctl0 gp_rdy0 gp_rdy1 gp_rdy2 gp_rdy3 gp_rdy4 gp_rdy5 gp_ctl5 gp_ctl4 gp_d11 gp_d12 gp_d13 gp_d15 gp_d14 gp_adr0 gp_adr1 gp_adr2 gp_adr3 gp_adr4 gp_adr5 aa3v3_io19 gp_sloe gp_wu2 gp_fifoadr0 gp_fifoadr1 gp_pktend usb_clk_o machxo_tms machxo_sleepn gp_int1 gpio_tdi gpio_tdo gpio_tms usbcf_wake gp_int0 gpio_tck usbcf_i2c_sda usbcf_i2c_scl jtag_prog jtag_trst jtag_done jtag_init machxo_tdi machxo_tdo machxo_tck machxo_tms ec_tms clk_machxo gp_ifclk gp_slcs# machxo_clk0 clk_machxo aa3v3_io20 aa3v3_io21 expcon_io40 expcon_io39 expcon_io41 expcon_io43 expcon_io44 expcon_io42 bb3v3_io3 bb3v3_io2 bb3v3_io1 bb3v3_io0 expcon_io[45:0] spido sispi cclk csspin hold# wp# wp# hpe_reset# usbcf_p usbcf_m pwr_in hpe_reset# usb_scl usb_sda vcc3v3 gnd vcc1v2 vcc3v3 vcc3v3 gnd vcc3v3 vcc3v3_conf gnda_conf gnd gnda_conf gndp vcc3v3 gnd gnd gnd vcc3v3 vcc3v3_conf gnda_conf gnd gnda_conf vcc3v3 gnd vcc3v3 gnd gnd vcc3v3 gnd gnd gnd vcc2v5 vcc3v3 gnd vcc2v5 gnd vcc2v5 gnd gnd gnd gnd vcc3v3 gnd vcc3v3 gnd gnd vcc3v3 vcc3v3 gnd vcc3v3 gnd vcc3v3 vcc3v3 gnd vcc3v3 machxo_io[6:0] 2 machxo_clk0 2 bb3v3_io[11:0] 2,9 clk_machxo 6 expcon_io[45:0] 2,9 hpe_reset# 2,6 usb_scl 7 usb_sda 7 : t e e h s : t c e j o r p authors: revision: created: last modified: ifw: of page f n o c _ a g p f _ 3 0 12 3 spi flash for configuration lattice lfec33 fpga (configuration) offpage m25p80vmw6p 8-megabit place the 4k7 resistors close to their clock line to keep the stub length as short as possi ble. usb-jtag programmer connector usb peripheral for configuration jtag connector for configuration sternpunkt an x2 cclk testpad area (rm2.54) of machxo 0 - cfg2 - slave p arallel mode 0 0 init# 1 1 1 1 done 1 1 spi master 1 0 0 0 0 spix master drain program# slave serial 1 - configuration settings source ispjtag sot-23 cfg0 0 master serial 1 0 master p arallel gate cfg1 gsrn 1% dout tp0319 r0302 10k0 1 2 tp0318 + c0324 4u70 1 2 ld0303 led yellow tp0337 tp0332 tp0303 fb0302 blm18pg600sn1 12 tp0325 tp0324 tp0349 100n c0309 r0315 4k70 1 2 tp0338 tp0333 tp0310 100n c0304 rj0304 0r00 1 2 tp0343 tp0330 tp0354 tp0339 tp0334 tp0316 100n c0322 tp0301 r0301 4k70 1 2 tp0348 100n c0310 1n00 c0315 r0314 10k0 1 2 r0306 470r 12 12p0 c0339 tp0340 tp0335 tp0322 100n c0303 tp0308 8 megabit spi flash u0305 m25p80vmw6p cs 1 do 2 wp 3 gnd 4 vcc 8 hold 7 clk 6 di 5 tp0306 t0301 bss138/sot 100n c0302 tp0341 tp0336 tp0328 100n c0311 tp0314 tp0351 rj0302 0r00 1 2 tp0342 tp0346 100n c0314 12p0 c0340 rj0303 nb_10k0 1 2 tp0320 1n00 c0301 rj0305 nb_10k0 1 2 ld0301 led blue 100n c0316 100n c0319 tp0304 x2 usb peripheral vcc 1 data- 2 data+ 3 gnd 4 shield 5 shield 6 100n c0312 r0307 4k70 1 2 tp0326 r0317 10k0 1 2 sw0302 cas-120a a 1 b 3 c 2 tp0311 q0301 24mhz 1 2 tp0359 t0302 bss138/sot fb0301 blm18bd601sn1 1 2 tp0344 tp0353 tp0350 rj0301 nb_10k0 1 2 1n00 c0323 tp0317 r0304 10k0 1 2 tp0302 100n c0317 configuration power supply u0201e lfecp/ec33-484bga csn/pb35b u12 cs1n/pb34b u11 writen/pb34a y12 di/csspin/pr54b v21 dout/cson/pr54a w22 busy/sispi/pr53b u21 pr53a/spid0/d7 v22 cfg2 t19 cfg1 u19 cfg0 u18 programn v18 cclk t20 initn t21 done r20 xres l3 pb40b/spid2/d5 v14 pb38b/spid4/d3 v13 pb37b/spid6/d1 ab12 pb41b/spid1/d6 ab13 pb39b/spid3/d4 u14 pb37a/spid5/d2 aa12 pb36b/spid7/d0 u13 tck t5 tdi u5 tms t4 tdo u1 vccj u2 vccaux g15 vccaux g16 vccaux g7 vccaux g8 vccaux h16 vccaux h7 vccaux r7 vccaux r16 vccaux t15 vccaux t16 vccaux t7 vccaux t8 vccpll j17 vccpll j6 vccpll p6 vccpll p17 nc a2 nc ab2 nc a21 gpio y21 r0316 10k0 1 2 tp0323 tp0309 tp0355 100n c0313 tp0329 tp0327 100n c0320 sw0301 b3fs-1010p 1 3 2 4 tp0347 100n c0308 tp0315 tp0357 tp0307 100n c0318 r0308 330r 12 tp0305 tp0356 rj0306 0r00 1 2 100n c0321 bank 0/0,1 bank 1/2,3 bank 2/4,5 bank 3/6,7 u0302 macxo-640/1200-132csbga pl2a b1 pl2b/pl3c c1 pl3a/pl3d c3 pl3b/pl4b d1 pl3d/pl4c d3 pl5a/pl6a e2 vccio1/vccio3 l12 (gsrn) pl5b/pl6b e3 pb5d/pb7c n8 pb5b/pb7b (pclkt) m7 pb5a/pb6f n7 sleepn n12 pb6a/pb7d p8 pb6b/pb7f (pclkt) m8 pb4f/pb6a m6 pb4e/pb5c n6 vcc p6 pb3b m4 pb3c/pb4a n4 gnd f1 vccio3/vccio7 d2 pl9b/pl12a k2 pb2c m3 pb2d n3 pl7c/pl10b h1 pl8a/pl11b j1 pl9a/pl11d j3 vccio1/vccio2 e12 vccio3/vccio6 k3 pl5d/pl6d f2 pl6b/pl7c f3 pl7a/pl8d g3 pl7b/pl10a h2 pr3c/pr4a d12 pr4d/pr6a f12 pr4c/pr5b e13 pr2b/pr3c c13 vccio0/vccio1 b11 pr2a/pr2a a14 pt9c/pt10f b12 pt5b/pt6f (pclkt) c8 pt5a/pt6d b7 pt6b/pt7d (pclkt) a8 pt6a/pt7b b8 pt4d/pt5d a6 pt4c/pt5c b6 gnd p9 pt3d/pt4b a5 vccaux p7 vcc h3 pt3b/pt3d a4 vccio0/vccio0 c5 vccio2/vccio4 m10 pt2f/pt3c c4 pt2d/pt3b a3 pt2c/pt2b a2 pt2b/pt3a b3 pt2a a1 pr11a/pr15a m12 pr10b/pr14b m13 pr8b/pr11b k12 pr8a/pr11a j13 pr10a/pr14a l14 pr7c/pr10b j12 pr7b/pr10a h14 pr7a/pr9b h13 pr6b/pr8a g14 vccio2/vccio5 n2 pr8d/pr12b k14 pr5d/pr6c f14 pr5c/pr6b f13 pr8c/pr12a k13 pr6d/pr9a h12 pr4b/pr5a e14 pr6c/pr8b g13 pr3d/pr4b d14 vcc g12 vcc c7 gnd j14 gnd c9 gndio0/gndio1 a10 gndio0/gndio0 b4 gndio1/gndio3 l13 gndio1/gndio2 d13 gndio2/gndio5 p2 gndio2/gndio4 n11 gndio3/gndio7 e1 gndio3/gndio6 l2 pl2c/pl2b b2 pl2d/pl4a c2 pl6c/pl7d g1 pl6d/pl8c g2 (tsall) pl8c/pl11c j2 pl9c/pl12b k1 pl10b/pl14b l3 pl10a/pl14a l1 pl11a/pl15a m1 pl11b/pl16a n1 pl11c/pl15b m2 pl11d/pl16b p1 pb3d/pb4b p5 pb7a/pb9a n9 pb7b/pb9b m9 pb7e/pb9c n10 pb7f/pb9d p10 pb8c/pb10a p11 pb8d/pb10b m11 pb9c/pb10c p12 pb9d/pb11c p13 pb9f/pb11d p14 tms p3 tck p4 tdo n5 tdi m5 pt3e/pt5a b5 pt3f/pt5b c6 pt7b/pt9b b9 pt7e/pt9e c10 pt7f/pt9f b10 pt8c/pt10c c11 pt7a/pt9a a9 pt9a/pt10d a11 pt9b/pt11a c12 pt9d/pt11c b13 pt9f/pt11d a13 pt9e/pt11b a12 pr2c/pr2b b14 pr2d/pr3d c14 pr11b/pr16a n13 pr11c/pr15b m14 pr11d/pr16b n14 vccaux a7 ld0302 led red tp0321 r0303 4k70 1 2 tp0313 tp0312 tp0358 u0301 cy7c68013a_tqfp100 vcc 1 vcc 33 vcc 38 vcc 49 vcc 53 vcc 66 vcc 78 vcc 85 vcc 20 gnd 2 gnd 21 gnd 39 gnd 48 gnd 50 gnd 65 gnd 75 gnd 94 gnd 99 avcc 16 agnd 19 agnd 12 avcc 9 pa0/int0 67 pa1/int1 68 pa2/sloe 69 pa3/wu2 70 pa4/fifoadr0 71 pa5/fifoadr1 72 pa6/pktend 73 pa7/flagd/slcs 74 pb0/fd0 34 pb1/fd1 35 pb2/fd2 36 pb3/fd3 37 pb4/fd4 44 pb5/fd5 45 pb6/fd6 46 pb7/fd7 47 pd0/fd8 80 pd1/fd9 81 pd2/fd10 82 pd3/fd11 83 pd4/fd12 95 pd5/fd13 96 pd6/fd14 97 pd7/fd15 98 pc0/gpifadr0 57 pc1/gpifadr1 58 pc2/gpifadr2 59 pc3/gpifadr3 60 pc4/gpifadr4 61 pc5/gpifadr5 62 pc6/gpifadr6 63 pc7/gpifadr7 64 pe0/t0out 86 pe1/t1out 87 pe2/t2out 88 pe3/rxd0out 89 pe4/rxd1out 90 pe5/int6 91 pe6/t2ex 92 pe7/gpifadr8 93 rdy0/slrd 3 rdy1/slwr 4 rdy2 5 rdy3 6 rdy4 7 rdy5 8 xtalin 11 xtalout 10 reset 77 nc 13 nc 14 nc 15 reserved 27 dplus 17 dminus 18 ctl0/flaga 54 ctl1/flagb 55 ctl2/flagc 56 ctl3 51 ctl4 52 ctl5 76 int4 22 int5 84 t0 23 t1 24 t2 25 wakeup 79 rxd0 41 txd0 40 rxd1 43 txd1 42 scl 29 sda 30 bkpt 28 clkout 100 ifclk 26 rd 31 wr 32 tp0331 tp0345 x3 con10 1 2 3 4 5 6 7 8 9 10 r0305 470r 12 + c0307 2u20 1 2 tp0352
36 latticemico32/dsp development board lattice semiconductor user? guide figure 14. 5 5 4 4 3 3 2 2 1 1 d d c c b b a a memory_a[22:0] memory_dq[31:0] flash_reset# flash_ry/by#_a flash_ry/by#_b sram_be0# sram_be1# sram_be2# sram_be3# sram_ce# memory_oe# memory_we# flash_ce# flash_wp#/acc flash_byte# ddr_dq[31:0] ddr_a[13:0] ddr_ck0+ ddr_ck0- ddr_dqs[3:0] ddr_dm[3:0] ddr_ck1+ ddr_ck1- ddr_cke0 ddr_cke1 ddr_ba0 ddr_ba1 ddr_we# ddr_ras# ddr_cas# ddr_s0# ddr_s1# ddr_vref ddr_dq8 ddr_dq9 ddr_ck0+ ddr_dq12 ddr_dq13 ddr_dm1 ddr_dq15 ddr_dq24 ddr_dq25 ddr_dq28 ddr_dq29 ddr_ck1+ sodimm_dq8 sodimm_dq9 sodimm_dqs1 sodimm_dq12 sodimm_dq13 sodimm_ck0+ sodimm_dq10 sodimm_dq14 sodimm_dq11 sodimm_dq15 ddr_dq14 ddr_dq11 ddr_dq10 sodimm_dq16 ddr_dq16 sodimm_dq0 sodimm_cke1 sodimm_a12 sodimm_a9 sodimm_a3 sodimm_a1 sodimm_a7 sodimm_a10 sodimm_ba1 sodimm_cke0 sodimm_a4 sodimm_a2 sodimm_a0 ddr_vtt ddr_vtt sodimm_dq4 sodimm_dq1 sodimm_dq5 ddr_vtt ddr_vtt ddr_vtt ddr_vtt ddr_vtt ddr_vtt ddr_vtt sodimm_a11 sodimm_a6 sodimm_a8 ddr_vtt ddr_vtt sodimm_a5 ddr_vref ddr_vtt sodimm_dq4 sodimm_dqs0 sodimm_dq1 sodimm_cke1 ddr_vref sodimm_a3 sodimm_dq24 sodimm_dq10 sodimm_dq8 sodimm_dq0 sodimm_a2 sodimm_a8 sodimm_we# sodimm_dq26 sodimm_dqs2 sodimm_dq14 sodimm_dm0 sodimm_dq3 sodimm_ba1 sodimm_dm3 sodimm_a9 sodimm_dq13 sodimm_ck1+ sodimm_dq30 sodimm_dq27 ddr_vtt sodimm_a7 sodimm_dq19 ddr_vref sodimm_cke0 sodimm_dq28 sodimm_a10 ddr_vtt sodimm_dq5 sodimm_dqs1 sodimm_dq29 sodimm_dm2 sodimm_a12 sodimm_dq12 sodimm_s1# sodimm_dm1 ddr_vref sodimm_dq20 sodimm_dq18 sodimm_dq23 sodimm_dq21 sodimm_ba0 sodimm_dq11 sodimm_ck1- sodimm_a4 sodimm_dq31 sodimm_a5 sodimm_dqs3 sodimm_dq25 sodimm_dq7 sodimm_dq2 sodimm_cas# sodimm_a13 sodimm_dq16 sodimm_dq17 sodimm_dq22 sodimm_s0# sodimm_a1 sodimm_ck0+ sodimm_a0 sodimm_a6 sodimm_dq15 sodimm_dq6 sodimm_ck0- sodimm_dq9 sodimm_ras# sodimm_a11 memory_we# memory_we# memory_dq31 memory_dq8 memory_dq30 memory_dq6 memory_dq12 memory_dq0 flash_byte# memory_oe# memory_dq31 memory_dq20 memory_dq19 flash_ce# memory_dq23 memory_dq12 flash_reset# memory_dq11 memory_dq27 sram_ce# memory_a[22:0] memory_dq[15:0] memory_dq13 memory_dq1 memory_dq28 memory_dq25 memory_dq27 memory_dq10 sram_be3# memory_dq[31:16] memory_dq19 memory_dq23 memory_dq4 memory_dq28 memory_dq11 memory_dq16 memory_dq8 flash_byte# memory_dq18 memory_dq7 memory_dq16 memory_dq25 memory_dq15 memory_dq2 memory_dq1 sram_be1# memory_oe# memory_dq4 memory_oe# memory_dq22 memory_dq3 memory_dq18 memory_a[22:0] memory_dq24 sram_be0# sram_ce# memory_dq3 memory_dq9 memory_dq21 memory_dq10 memory_we# memory_oe# memory_dq14 memory_dq5 memory_dq21 memory_dq30 memory_dq[15:0] memory_we# memory_dq9 memory_dq29 sram_be2# memory_dq5 memory_dq6 memory_dq15 memory_dq29 memory_a[17:0] memory_dq[31:16] memory_dq14 flash_reset# memory_dq7 memory_dq26 memory_dq24 memory_dq26 memory_dq17 memory_dq0 memory_dq22 flash_ce# memory_dq13 memory_dq2 flash_wp#/acc memory_dq20 memory_dq17 memory_a[17:0] memory_a17 memory_a2 memory_a3 memory_a11 memory_a22 memory_a1 memory_a2 memory_a13 memory_a4 memory_a5 memory_a15 memory_a21 memory_a1 memory_a20 memory_a15 memory_a5 memory_a8 memory_a10 memory_a18 memory_a16 memory_a9 memory_a13 memory_a15 memory_a9 memory_a4 memory_a7 memory_a19 memory_a1 memory_a6 memory_a16 memory_a16 memory_a3 memory_a3 memory_a5 memory_a7 memory_a5 memory_a12 memory_a15 memory_a21 memory_a17 memory_a2 memory_a13 memory_a4 memory_a7 memory_a12 memory_a10 memory_a10 memory_a19 memory_a6 memory_a20 memory_a12 memory_a0 memory_a6 memory_a2 memory_a13 memory_a4 memory_a8 memory_a6 memory_a17 memory_a3 memory_a8 memory_a17 memory_a10 memory_a11 memory_a14 memory_a16 memory_a14 memory_a11 memory_a18 memory_a14 memory_a9 memory_a8 memory_a0 memory_a9 memory_a7 memory_a12 memory_a0 memory_a1 memory_a11 memory_a0 memory_a22 memory_a14 sodimm_dq28 sodimm_dq25 sodimm_dq24 sodimm_dq29 sodimm_dqs0 ddr_dqs0 sodimm_dm0 ddr_dm0 sodimm_dq2 ddr_dq2 sodimm_dq6 ddr_dq6 sodimm_dq3 ddr_dq3 sodimm_dq7 ddr_dq7 sodimm_dm1 ddr_dqs1 sodimm_ck0- ddr_ck0- ddr_dq20 sodimm_dq20 sodimm_dq17 sodimm_dq21 ddr_dq17 ddr_dq21 sodimm_dqs2 ddr_dqs2 ddr_dm2 sodimm_dq18 sodimm_dq22 ddr_dq18 ddr_dq22 sodimm_dq19 sodimm_dq23 ddr_dq19 ddr_dq23 sodimm_dm2 sodimm_dqs3 ddr_dqs3 sodimm_dq26 sodimm_dq30 ddr_dq26 ddr_dq30 sodimm_dq27 ddr_dq27 sodimm_dq31 ddr_dq31 sodimm_dm3 ddr_dm3 sodimm_ck1- sodimm_ck1+ ddr_ck1- sodimm_dqs0 sodimm_we# sodimm_s0# sodimm_cas# sodimm_s1# sodimm_a13 ddr_cas# ddr_s1# ddr_we# ddr_s0# ddr_a13 ddr_ras# ddr_ba0 sodimm_ba0 sodimm_ras# sodimm_a1 sodimm_a3 sodimm_a0 sodimm_a2 sodimm_a10 sodimm_ba1 ddr_a2 ddr_a0 ddr_a3 ddr_a1 ddr_ba1 ddr_a10 ddr_a4 ddr_a5 sodimm_a5 sodimm_a4 ddr_a11 ddr_a8 ddr_a12 ddr_a9 ddr_a6 ddr_a7 sodimm_a12 sodimm_a9 sodimm_a8 sodimm_a11 sodimm_a7 sodimm_a6 ddr_cke0 ddr_cke1 sodimm_cke0 sodimm_cke1 sodimm_dm0 sodimm_dq2 sodimm_dq6 sodimm_dq3 sodimm_dq7 sodimm_dq8 sodimm_dq12 sodimm_dq9 sodimm_dq13 ddr_vtt sodimm_dqs1 sodimm_dm1 sodimm_dq10 sodimm_dq14 sodimm_dq11 sodimm_dq15 sodimm_dqs2 sodimm_dm2 sodimm_dq16 sodimm_dq20 sodimm_dq17 sodimm_dq21 sodimm_dq18 sodimm_dq19 sodimm_dq22 sodimm_dq23 sodimm_dqs3 sodimm_dm3 sodimm_dq24 sodimm_dq28 sodimm_dq25 sodimm_dq29 sodimm_dq26 sodimm_dq27 sodimm_dq30 sodimm_dq31 ddr_vtt ddr_vtt sodimm_we# sodimm_a13 sodimm_ba0 sodimm_s0# sodimm_ras# sodimm_cas# sodimm_s1# sodimm_dq0 ddr_dq0 sodimm_dq1 sodimm_dq4 sodimm_dq5 ddr_dq1 ddr_dq4 ddr_dq5 flash_wp#/acc flash_ry/by#_a flash_ry/by#_b vcc2v5 vcc2v5 vcc2v5 gnd gnd vcc3v3 gnd vcc3v3 gnd gnd gnd gnd gnd vcc3v3 vcc3v3 gnd gnd gnd vcc3v3 vcc3v3 gnd gnd vcc3v3 vcc3v3 memory_a[22:0] 2 memory_dq[31:0] 2 flash_reset# 2 flash_ry/by#_a 2 flash_ry/by#_b 2 sram_be0# 2 sram_be1# 2 sram_be2# 2 sram_be3# 2 sram_ce# 2 memory_oe# 2 memory_we# 2 flash_ce# 2 flash_wp#/acc 2 flash_byte# 2 ddr_dq[31:0] 2 ddr_a[13:0] 2 ddr_ck0+ 2 ddr_ck0- 2 ddr_dqs[3:0] 2 ddr_dm[3:0] 2 ddr_ck1+ 2 ddr_ck1- 2 ddr_cke0 2 ddr_cke1 2 ddr_ba0 2 ddr_ba1 2 ddr_we# 2 ddr_ras# 2 ddr_cas# 2 ddr_s0# 2 ddr_s1# 2 ddr_vref 2 : t e e h s : t c e j o r p authors: revision: created: last modified: ifw: of page 04_memory 12 4 offpage parallel flash async. sram high async. sram low sram flash high flash low ddr sdram socket (32 bit data bus) series resi stors parallel termination resistors - place c0401 as close as possible to the pvin pin - place c0403 as close as possible to the vref pin - place a bulk cap (100-220 f) capacitor at each end of the vtt island. (c04??, c04??) (2 x 4 mbit organized as 256k words of 32 bits) (2 x 128 mbit organized as 8m words of 32 bits) samsung k6r4016v1d-tc10 samsung k6r4016v1d-tc10 macronix macronix r0410 22r0 1 2 c0405 100n 1 2 r0422 10k0 r0405 22r0 1 2 100n c0415 r0414 33r0 12 rn04061 cn1j 4 jta 22r 1 2 3 4 8 7 6 5 rn0414 cnd1j 10k jta 33r 1 2 3 4 5 6 7 8 9 10 rn04021 cn1j 4 jta 22r 1 2 3 4 8 7 6 5 r0419 33r0 12 u0401 lp2995mr nc 1 gnd 2 vsense 3 vref 4 vtt 8 pvin 7 avin 6 vddq 5 128 megabit (x16) u0403 mx29lv128m h/l a0 31 a1 26 a2 25 a3 24 a4 23 a5 22 a6 21 a7 20 a8 10 a9 9 a10 8 a11 7 a12 6 a13 5 a14 4 a15 3 a16 54 a17 19 vcc 43 dq0 35 dq1 37 dq2 39 dq3 41 dq4 44 dq5 46 dq6 48 dq7 50 dq8 36 dq9 38 dq10 40 dq11 42 dq12 45 dq13 47 dq14 49 dq15/a-1 51 vss 52 vss 33 we# 13 reset# 14 ce# 32 ry/by# 17 oe# 34 a18 18 a19 11 a20 12 a21 15 vio 29 wp#/acc 16 a22 2 byte# 53 nc 30 nc 1 nc 27 nc 28 nc 55 nc 56 c0411 100n 1 2 rn04032 cn1j 4 jta 22r 1 2 3 4 8 7 6 5 c0404 100n 1 2 100n c0417 rn0412 cnd1j 10k jta 33r 1 2 3 4 56 7 8 9 10 r0420 33r0 12 r0411 22r0 12 c0410 100n 1 2 100n c0421 47u c0401 r0401 22r0 1 2 100n c0418 x4b ddr_sodimm200 dq16 41 dq17 43 vdd 45 dqs2 47 dq18 49 vss 51 dq19 53 dq24 55 vdd 57 dq25 59 dqs3 61 vss 63 dq26 65 dq27 67 vdd 69 cb0/nc 71 cb1/nc 73 vss 75 dqs8/nc 77 cb2/nc 79 vdd 81 cb3/nc 83 nc 85 vss 87 ck2+/nc 89 ck2-/nc 91 vdd 93 cke1/nc 95 nc 97 a12/nc 99 a9 101 vss 103 a7 105 a5 107 a3 109 a1 111 vdd 113 a10/ap 115 ba0 117 we# 119 s0# 121 a13/nc 123 vss 125 dq32 127 dq33 129 vdd 131 dqs4 133 dq34 135 vss 137 dq35 139 dq40 141 vdd 143 dq41 145 dqs5 147 vss 149 dq42 151 dq43 153 vdd 155 vss 161 dq48 163 dq49 165 vdd 167 dqs6 169 dq50 171 vss 173 dq51 175 dq56 177 vdd 179 dq57 181 dqs7 183 vss 185 dq58 187 dq59 189 vdd 191 sda 193 scl 195 vddspd 197 vddid 199 dq20 42 dq21 44 vdd 46 dm2 48 dq22 50 vss 52 dq23 54 dq28 56 vdd 58 dq29 60 dm3 62 vss 64 dq30 66 dq31 68 vdd 70 cb4/nc 72 cb5/nc 74 vss 76 dm8/nc 78 cb7/nc 84 nc 86 vss 88 vss 90 vdd 92 vdd 94 cke0 96 nc 98 a11 100 a8 102 vss 104 a6 106 a4 108 a2 110 a0 112 vdd 114 ba1 116 ras# 118 cas# 120 s1#/nc 122 nc 124 vss 126 dq36 128 dq37 130 vdd 132 dm4 134 dq38 136 vss 138 dq39 140 dq44 142 vdd 144 dq45 146 dm5 148 vss 150 dq46 152 dq47 154 vdd 156 ck1- 158 ck1+ 160 vss 162 dq52 164 dq53 166 vdd 168 dm6 170 dq54 172 vss 174 dq55 176 dq60 178 vdd 180 dq61 182 dm7 184 vss 186 dq62 188 dq63 190 vdd 192 sa0 194 vdd 157 vss 159 sa2 198 nc 200 sa1 196 cb6/nc 80 vdd 82 rn04041 cn1j 4 jta 22r 1 2 3 4 8 7 6 5 rn0413 cnd1j 10k jta 33r 1 2 3 4 56 7 8 9 10 rn04022 cn1j 4 jta 22r 1 2 3 4 8 7 6 5 220u c0416 rn04062 cn1j 4 jta 22r 1 2 3 4 8 7 6 5 rn04012 cn1j 4 jta 22r 1 2 3 4 8 7 6 5 100n c0412 r0406 22r0 1 2 r0412 22r0 12 r0407 22r0 1 2 x4a ddr_sodimm200 vref 1 vss 3 dq0 5 dq1 7 vdd 9 dqs0 11 dq2 13 vss 15 dq3 17 dq8 19 vdd 21 dq9 23 dqs1 25 vss 27 dq10 29 dq11 31 vdd 33 ck0+ 35 ck0- 37 vss 39 vref 2 vss 4 dq4 6 dq5 8 vdd 10 dm0 12 dq6 14 vss 16 dq7 18 dq12 20 vdd 22 dq13 24 dm1 26 vss 28 dq14 30 dq15 32 vdd 34 vdd 36 vss 38 vss 40 r0417 33r0 12 r0404 22r0 12 100n c0422 r0421 10k0 100n c0419 r0413 33r0 12 u0405 sram_tsop44_2 a0 1 a1 2 a2 3 a3 4 a4 5 a5 18 a6 19 a7 20 a8 21 a9 22 a10 23 a11 24 a12 25 a13 26 a14 27 a15 42 a16 43 a17 44 io1 7 io2 8 io3 9 io4 10 io5 13 io6 14 io7 15 io8 16 io9 29 io10 30 io11 31 io12 32 io13 35 io14 36 io15 37 io16 38 cs# 6 oe# 41 we# 17 ub# 40 lb# 39 vcc 11 vcc 33 gnd 12 gnd 34 100n c0403 100n c0414 r0418 33r0 12 r0409 22r0 12 rn04071 cn1j 4 jta 22r 1 2 3 4 8 7 6 5 r0402 22r0 12 c0407 100n 1 2 c0409 100n 1 2 rn04051 cn1j 4 jta 22r 1 2 3 4 8 7 6 5 rn04042 cn1j 4 jta 22r 1 2 3 4 8 7 6 5 rn0409 cnd1j 10k jta 33r 1 2 3 4 56 7 8 9 10 rn04072 cn1j 4 jta 22r 1 2 3 4 8 7 6 5 r0415 33r0 12 u0404 sram_tsop44_2 a0 1 a1 2 a2 3 a3 4 a4 5 a5 18 a6 19 a7 20 a8 21 a9 22 a10 23 a11 24 a12 25 a13 26 a14 27 a15 42 a16 43 a17 44 io1 7 io2 8 io3 9 io4 10 io5 13 io6 14 io7 15 io8 16 io9 29 io10 30 io11 31 io12 32 io13 35 io14 36 io15 37 io16 38 cs# 6 oe# 41 we# 17 ub# 40 lb# 39 vcc 11 vcc 33 gnd 12 gnd 34 220u c0402 100n c0420 100n c0413 rn0410 cnd1j 10k jta 33r 1 2 3 4 56 7 8 9 10 c0406 100n 1 2 c0408 100n 1 2 rn04031 cn1j 4 jta 22r 1 2 3 4 8 7 6 5 r0416 33r0 12 rn04011 cn1j 4 jta 22r 1 2 3 4 8 7 6 5 128 megabit (x16) u0402 mx29lv128m h/l a0 31 a1 26 a2 25 a3 24 a4 23 a5 22 a6 21 a7 20 a8 10 a9 9 a10 8 a11 7 a12 6 a13 5 a14 4 a15 3 a16 54 a17 19 vcc 43 dq0 35 dq1 37 dq2 39 dq3 41 dq4 44 dq5 46 dq6 48 dq7 50 dq8 36 dq9 38 dq10 40 dq11 42 dq12 45 dq13 47 dq14 49 dq15/a-1 51 vss 52 vss 33 we# 13 reset# 14 ce# 32 ry/by# 17 oe# 34 a18 18 a19 11 a20 12 a21 15 vio 29 wp#/acc 16 a22 2 byte# 53 nc 30 nc 1 nc 27 nc 28 nc 55 nc 56 rn0408 cnd1j 10k jta 33r 1 2 3 4 56 7 8 9 10 r0408 22r0 12 r0403 22r0 12 rn0411 cnd1j 10k jta 33r 1 2 3 4 56 7 8 9 10 rn04052 cn1j 4 jta 22r 1 2 3 4 8 7 6 5
37 latticemico32/dsp development board lattice semiconductor user? guide figure 15. 5 5 4 4 3 3 2 2 1 1 d d c c b b a a seg_ca0#_b seg_ca0# seg_ca1#_b seg_ca1# lcd_cont dsw3 dsw0 dsw1 dsw2 seg_c#_x seg_d#_x seg_e#_x seg_f#_x seg_g#_x seg_dp#_x seg_a# seg_c# seg_e# seg_g# seg_b# seg_d# seg_f# seg_dp# tst_row0 seg_c# seg_e# seg_g# seg_d# seg_f# seg_dp# tst_row2 tst_row3 lcd_enable lcd_regsel lcd_rw led0# tst_step led1# led2# led3# led4# led5# seg_ca1#_x seg_ca0#_x led6# led7# tst_row1 tst_col2 tst_col1 seg_ca0# seg_a# seg_b# seg_c# seg_d# seg_e# seg_f# seg_dp# dsw0 dsw1 dsw2 dsw3 seg_ca1# seg_g# tst_step tst_col0 tst_col2 tst_col1 led7# led0# led1# led2# led3# led4# led5# led6# tst_row0 tst_row3 tst_row2 tst_row1 lcd_regsel lcd_rw lcd_enable seg_b#_x seg_a#_x seg_b# seg_a# tst_col0 vcc3v3 vcc3v3 vcc3v3 vcc3v3 vcc3v3 vcc5v0 vcc5v0 gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd vcc5v0 dsw0 2 dsw1 2 dsw2 2 dsw3 2 tst_row0 2 tst_row1 2 tst_row2 2 led0# 2 tst_row3 2 led2# 2 led1# 2 led3# 2 led5# 2 led4# 2 led6# 2 seg_ca0# 2 led7# 2 seg_b# 2 seg_ca1# 2 seg_c# 2 seg_e# 2 seg_f# 2 seg_g# 2 seg_a# 2 seg_dp# 2 tst_col0 2 seg_d# 2 tst_col1 2 tst_step 2 tst_col2 2 lcd_regsel 2 lcd_rw 2 lcd_enable 2 : t e e h s : t c e j o r p authors: revision: created: last modified: ifw: of page y e k _ d e l _ 5 0 12 5 8x led single step key lcd connector lcd backlight on/off key matrix 7-segment display 4x dip switch offpage display contrast tp0507 nb_test point 1 r0523 1k00 1 2 sw0514 sw dip-4 ld0502 led red r0507 330r 12 r0510 100k tp0508 nb_test point 1 sw0502 b3fs-1010p 13 24 ld0507 led red r0501 330r 12 d0506 mmbd4148 sw0504 b3fs-1010p 13 24 d0508 mmbd4148 d0510 mmbd4148 d0512 mmbd4148 r0522 120r 1 2 tp0509 nb_test point 1 rp0502 10k0 18 27 3 6 45 d0501 mmbd4148 sw0508 b3fs-1010p 1 3 24 r0502 330r 12 100n c0501 r0505 330r 12 r0506 330r 12 d0502 mmbd4148 r0516 120r 1 2 d0504 mmbd4148 q0502 bc807-25 1 2 3 sw0511 b3fs-1010p 13 24 tp0502 nb_test point 1 tp0501 nb_test point 1 nc u0501 74ahc1g14_sot353 4 1 2 5 3 rp0501 1k0 18 27 36 4 5 sw0507 b3fs-1010p 13 24 r0508 330r 12 sw0510 b3fs-1010p 13 24 tp0503 nb_test point 1 r0517 1k00 1 2 ld0503 led red sw0505 b3fs-1010p 1 3 24 ld0508 led red r0521 120r 1 2 r0519 120r 1 2 r0525 1k00 1 2 tp0504 nb_test point 1 r0515 120r 1 2 a b c d e f g dp d1 d2 u0502 eld-426gwa d 1 dp 2 e 3 c 4 c.a. d2 5 b 6 a 7 f 8 g 9 c.a. d1 10 r0518 120r 1 2 sw0503 b3fs-1010p 13 24 r0520 120r 1 2 d0509 mmbd4148 ld0506 led red d0507 mmbd4148 d0511 mmbd4148 tp0505 nb_test point 1 q0501 bc807-25 1 2 3 r0509 100k x6 con16a 12 3 4 56 78 9 10 11 12 13 14 15 16 r0513 1k00 1 2 r0504 330r 12 tp0506 nb_test point 1 sw0501 b3fs-1010p 13 24 x5 hdr2 1 2 d0503 mmbd4148 d0505 mmbd4148 sw0513 b3fs-1010p 13 24 sw0512 b3fs-1010p 1 3 2 4 r0526 5k r0524 10k0 1 2 ld0505 led red r0511 1k00 1 2 ld0504 led red sw0506 b3fs-1010p 13 24 sw0509 b3fs-1010p 1 3 24 r0503 330r 12 ld0501 led red r0512 1k00 1 2 r0514 120r 1 2
38 latticemico32/dsp development board lattice semiconductor user? guide figure 16. 5 5 4 4 3 3 2 2 1 1 d d c c b b a a hpe_reset# cat_vsense cat_reset# cat_reset cat_i2c_sda cat_i2c_scl cat_i2c_scl cat_i2c_sda i2c_scl1 i2c_sda1 i2c_scl1 i2c_sda1 clk_fpga clk_eth clk_fpga clk_eth hpe_reset# hpe_resout# hpe_resout# expcon_osc clk expcon_osc clk_machxo clk_machxo vcc3v3 vcc3v3 vcc3v3 vcc3v3 vcc3v3 gnd gnd gnd gnd gnd gnd gnd vcc3v3 gnd vcc3v3 vcc3v3_osc vcc3v3_osc vcc3v3_osc gnd vcc5v0 i2c_sda1 2 i2c_scl1 2 clk_fpga 2 clk_eth 8 hpe_reset# 2,3 hpe_resout# 2,7,8,9 expcon_osc 9 clk_machxo 3 : t e e h s : t c e j o r p authors: revision: created: last modified: ifw: of page t e s e r _ k c o l c _ 6 0 12 6 ext. reset reset button reset control clock sources 1.25 v rp of the i2c bus rs of the i2c bus clk offpage vth = 1.25v x (r0601+r 0602)/r0602 = 4.4v r0614 33r0 sw0601 b3fs-1010p 1 3 2 4 fb0601 blm21pg331sn1d 12 r0611 22r0 100n c0601 tp0601 test point 1 u0601 cat1026si-30 vlow 1 reset 2 vsense 3 gnd 4 sda 5 scl 6 reset 7 vcc 8 d0601 bat54a 3 1 2 nc u0602 74ahc1g14_sot353 4 1 2 5 3 r0603 10k0 r0602 10k7 u0604 cy2304nz_tssop8 buf_in 1 oe 2 out1 3 gnd 4 out4 8 out3 7 vdd 6 out2 5 x7 nb_hdr2 1 2 r0610 22r0 100n c0604 r0615 33r0 r0605 10k0 r0606 nb_10k0 1 2 r0608 2k7 r0607 nb_10k0 1 2 u0603 osc_smt4_25mhz en 1 gnd 2 clk 3 vcc 4 r0609 2k7 r0612 33r0 1n00 c0602 r0601 27k0 r0604 100k r0613 33r0 100n c0603
39 latticemico32/dsp development board lattice semiconductor user? guide figure 17. 5 5 4 4 3 3 2 2 1 1 d d c c b b a a rs_cts_lvttl rs_cts_lvttl rs_rxd_lvttl rs_rxd_lvttl rs_txd_lvttl rs_rts_lvttl rs_txd_lvttl rs_rts_lvttl usb_xtalin usb_xtalout usb_gpio[28:0] hpe_resout# usb_dm2a usb_dp2a usb_dm2b usb_dp2b usb_otg_dm1a usb_otg_dp1a usb_dm1b usb_dp1b usb_gpio28 usb_gpio13 usb_sda usb_scl usb_gpio8 usb_gpio0 usb_gpio19 usb_gpio11 usb_gpio15 usb_gpio10 usb_gpio12 usb_gpio6 usb_gpio7 usb_otg_id usb_gpio5 usb_gpio18 usb_gpio3 usb_gpio25 usb_gpio21 usb_gpio17 usb_gpio1 usb_gpio4 usb_gpio22 usb_gpio26 usb_gpio20 usb_gpio14 usb_gpio9 usb_gpio23 usb_gpio24 usb_gpio2 usb_gpio27 usb_gpio16 usb_sda usb_scl usb_pwen0 usb_vbus0 usb_pwen1 usb_pwen2 usb_vbus1 usb_vbus0_x usb_vbus1_x usb_vbus2_x usb_vbus2 usb_gpio[28:0] hpe_resout# usb_pwen0 usb_oc0# usb_pwen1 usb_oc1# usb_pwen2 usb_oc2# usb_oc0# usb_oc1# usb_oc2# usb_miso usb_cts usb_txd usb_mosi usb_ssi# usb_sck usb_miso usb_ssi# usb_sck usb_mosi usb_txd usb_cts usb_scl usb_sda usb_otg_dm1a usb_otg_dp1a usb_otg_vbus_x usb_otg_vbus usb_otg_vbus usb_otg_id rs_dcd_lvttl_x rs_txd_lvttl_x rs_dsp_lvttl_x rs_cts_lvttl_x rs_dtp_lvttl_x rs_rts_lvttl_x rs_rxd_lvttl_x usb_a15 usb_rts usb_rxd usb_rts usb_rxd usb_dm2b usb_vbus2_x usb_dp1b usb_dm1b usb_dm2a usb_dp2b usb_dp2a usb_vbus0_x usb_vbus1_x vcc3v3 vcc3v3 gnd gnd gnd gnd gnd vcc3v3 vcc3v3 gnd gnd gnda_usb vcc3v3_usb vcc3v3 gnd vcc3v3 vcc3v3 gnda_usb vcc5v0 gnda_usb gnda_usb gnda_usb vcc5v0 gnda_usb gnda_usb gnda_usb vcc3v3_usb gnda_usb gnda_usb gndp gnda_usb vcc3v3 vcc3v3 vcc3v3 gnd gnda_usb gnd gnd vcc3v3 gnd gnd rs_cts_lvttl 2 rs_rxd_lvttl 2 rs_txd_lvttl 2 rs_rts_lvttl 2 usb_gpio[28:0] 2 hpe_resout# 2,6,8,9 usb_pwen0 2 usb_oc0# 2 usb_pwen1 2 usb_oc1# 2 usb_pwen2 2 usb_oc2# 2 usb_miso 2 usb_ssi# 2 usb_sck 2 usb_mosi 2 usb_txd 2 usb_cts 2 usb_scl 3 usb_sda 3 usb_rts 2 usb_rxd 2 : t e e h s : t c e j o r p authors: revision: created: last modified: ifw: of page 07_serial_usb 12 7 offpage rs232 interface usb controller gpio30 gpio31 boot configurat ion interface host port inte rface (hpi) high-speed s erial (hss) serial peripheral interface (spi) i2c eeprom (sta ndalone mode) 00 1 0 1 0 11 sda scl 1500ma 330 ohm @ 100 mhz usb otg usb host usb host usb host c0707 1u00 100n c0701 ext memory ext memory con trol gpio usb ports charge pump reset / clock power u0702 cy7c67300_tqfp100 a1 1 a2 2 a4 7 a3 3 a6 17 a5 8 a8 24 a9 25 a7 20 a10 27 a11 30 a12 31 a13 32 a14 33 a15/clksel 38 a16 97 a17 95 a18 96 d0 83 a0/bel 99 d1 82 d2 81 d3 80 d4 79 d5 78 d6 77 d7 76 d8/miso 74 d9/ssi 73 d10/sck 72 d11/mosi 71 d12/txd 70 d13/rxd 69 d14/rts 68 d15/cts 67 beh 98 wr 64 rd 62 memsel 34 romsel 35 ramsel 36 gpio0/d0 94 gpio1/d1 93 gpio2/d2 92 gpio3/d3 91 gpio4/d4 90 gpio8/miso/d8 66 gpio7/d7 86 gpio6/d6 87 gpio9/ssi/d9 65 gpio5/d5 89 gpio10/sck/d10 61 gpio11/mosi/d11 60 gpio12/d12 59 gpio13/d13 58 gpio14/d14 57 gpio15/ssi/d15 56 gpio16/txd/i_a0 55 gpio17/rxd/i_a1 54 gpio18/rts/i_a2 53 gpio19/cs0/h_a0 52 gpio20/cs1/h_a1 50 gpio21/ncs 49 gpio22/wr/iow 48 gpio23/rd/ior 47 gpio24/int/iordy 46 gpio25 45 gpio26/cts/pwm3 44 gpio27/rx 43 gpio28/tx 42 gpio29/otgid 41 gpio30/scl 40 gpio31/sda 39 vcc 88 vcc 63 vcc 37 gnd 100 gnd 75 gnd 51 gnd 26 dm1a 22 dp1a 23 dp1b 19 dm1b 18 dm2b 4 dp2a 10 dm2a 9 dp2b 5 avcc 21 agnd 6 xtalin 29 xtalout 28 reset 85 reserved 84 boostvcc 16 vswitch 14 boostgnd 15 otgvbus 11 cswitcha 13 cswitchb 12 r0704 10k0 1 2 x10b usb_typea/host vcc 1b data- 2b data+ 3b gnd 4b shield 15 shield 16 q0701 crystal_12mhz 12 rj0701 nb_10k0 1 2 10u0 c0717 100n c0719 nb_100n c0727 rj0704 0r00 1 2 r0705 10k0 1 2 100n c0703 100n c0714 d0701 bat54s 3 1 2 fb0704 blm18pg600sn1 12 r0701 0r00 12 fb0705 blm21pg331sn1d 1 2 x10c usb_typea/host vcc 1c data- 2c data+ 3c gnd 4c x8 con_dsub_9m 1 6 2 7 3 8 4 9 5 + c0713 100u u0704 sp2526-1en ena 1 flga 2 flgb 3 enb 4 outb 5 gnd 6 in 7 outa 8 c0715 22p0 100n c0711 100n c0705 100n c0709 fb0703 blm21pg331sn1d 1 2 r0703 47k0 12 c0716 22p0 100n c0721 r0707 10k0 1 2 100n c0704 + c0710 100u 10u0 c0702 100n c0720 r0706 15k0 1 2 c0726 4u70 r0702 0r00 1 2 + c0708 100u u0701 max3232/tssop c1+ 1 c1- 3 c2+ 4 c2- 5 v+ 2 v- 6 t1in 11 t2in 10 r1in 13 r2in 8 t1out 14 t2out 7 r1out 12 r2out 9 vcc 16 gnd 15 c0712 1u00 rj0703 nb_10k0 1 2 u0703 sp2526-1en ena 1 flga 2 flgb 3 enb 4 outb 5 gnd 6 in 7 outa 8 100n c0724 fb0702 blm21pg331sn1d 12 x9 usb miniab 440479-1 vbus 1 d- 2 d+ 3 id 4 gnd 5 sh1 6 sh2 7 sh3 8 sh4 9 r0708 nb_1m00 12 100n c0706 fb0701 blm21pg331sn1d 12 c0725 100n x10a usb_typea/host vcc 1a data- 2a data+ 3a gnd 4a shield 13 shield 14 1n00 c0723 100n c0722 100n c0718 rj0702 0r00 1 2
40 latticemico32/dsp development board lattice semiconductor user? guide figure 18. 5 5 4 4 3 3 2 2 1 1 d d c c b b a a eth_txd0 eth_txclk0 eth_rxer eth_rxd3 eth_rxd2 eth_rxd0 eth_rxclk0 eth_rxdv eth_crs eth_col eth_mdio eth_rxd1 eth_tx- eth_rx- clk_eth eth_rx+ lan_tx+ eth_mdintr# eth_cfg3 eth_cfg1 eth_cfg3 lan_tx- lan_rx+ lan_rx- eth_txer eth_txd3 eth_txd1 eth_txd0 eth_txen eth_txclk eth_rxer eth_rxd3 eth_rxd2 eth_rxd0 eth_rxclk eth_rxdv eth_crs eth_col eth_rxd1 eth_txd2 eth_mdc eth_mdio eth_mdintr# eth_tx+ eth_txclk eth_rxclk eth_txd1 eth_txd2 eth_txd3 eth_txen eth_txer eth_mdc hpe_resout# hpe_resout# eth_cfg2 eth_cfg1 eth_cfg2 clk_eth vcc3v3 vcc3v3_lan vcc3v3_lan vcc3v3 vcc3v3_lan vcc3v3 vcc3v3 gnd gnd gnd_lan gnd_lan gnd gnd gnd gndp gnd gnd vcc3v3 vcc3v3 vcc3v3 gnd_lan gndp gnd eth_txer 2 eth_txd3 2 eth_txd2 2 eth_txd1 2 eth_txd0 2 eth_txen 2 eth_txclk 2 eth_rxer 2 eth_rxd3 2 eth_rxd2 2 eth_rxd1 2 eth_rxd0 2 eth_rxclk 2 eth_rxdv 2 eth_crs 2 eth_col 2 eth_mdintr# 2 eth_mdc 2 eth_mdio 2 hpe_resout# 2,6,7,9 clk_eth 6 : t e e h s : t c e j o r p authors: revision: created: last modified: ifw: of page t e n r e h t e _ 8 0 12 8 offpage ethernet 2kv 2kv 2kv txslew1 txslew0 0 1 0 1 1 0 1 0 slew rate 2.5ns 3.1ns 3.7ns 4.3ns r0810 49r9 1 2 c0806 1n00 1 2 r0808 49r9 12 r0816 22k1 1 2 r0801 220r 12 r0813 220r 12 r0802 22r0 1 2 c0801 270p 1 2 c0802 270p 1 2 r0805 nb_10k0 1 2 r0818 10k0 12 r0804 nb_10k0 1 2 c0810 220n 1 2 led0801 led red 1 2 rj0805 nb_10k0 1 2 c0805 10n0 1 2 rj0803 nb_10k0 1 2 r0809 49r9 1 2 c0809 220n 1 2 u0802 pulse h1112 rd+ 5 rd- 6 ct_rd 4 td+ 1 td- 2 ct_td 3 rx+ 8 rx- 7 ct_rx 9 tx+ 12 tx- 11 ct_tx 10 r0807 49r9 12 c0804 100n 1 2 r0817 10k0 12 c0807 1n00 1 2 r0815 49r9 1 2 u0801 lxt971a tx_er 54 txd3 60 txd2 59 txd1 58 txd0 57 tx_en 56 tx_clk 55 mdc 43 mdio 42 rxd3 45 rxd2 46 rxd1 47 rxd0 48 mdint# 64 rx_clk 52 crs 63 col 62 rx_dv 49 rx_er 53 reset# 4 tpfop 19 tpfon 20 tpfip 23 tpfin 24 led/cfg1 38 pwrdwn 39 vccd 51 vccio 8 vccio 40 vcca 21 dgnd 7 dgnd 11 dgnd 18 addr4 16 tdi 27 refclk/xi 1 xo 2 mddis 3 vcca 22 dgnd 25 dgnd 41 dgnd 50 dgnd 61 sd/tp 26 txslew0 5 txslew1 6 rbias 17 led/cfg2 37 led/cfg3 36 tdo 28 tms 29 tck 30 trst 31 addr3 15 addr2 14 addr1 13 addr0 12 pause 33 sleep 32 test0 34 test1 35 nc 9 nc 10 nc 44 rp0802 10k0 18 27 36 45 c0803 100n 1 2 rp0801 10k0 18 27 36 45 c0813 10n0 1 2 r0806 22r0 1 2 fb0802 blm18pg600sn1 12 rj0806 10k0 12 r0812 49r9 1 2 r0811 49r9 1 2 x11 rj-45-led tx+ 1 tx- 2 rx+ 3 nc 4 nc 5 rx- 6 nc 7 nc 8 shield 13 shield 14 led2- 10 led2+ 9 led1- 12 led1+ 11 r0814 49r9 1 2 c0808 1n00 1 2 rj0801 nb_10k0 1 2 fb0801 blm11b750s 12 rj0804 10k0 12 r0803 220r 12 rj0802 10k0 12
41 latticemico32/dsp development board lattice semiconductor user? guide figure 19. 5 5 4 4 3 3 2 2 1 1 d d c c b b a a expcon_io1 expcon_io3 expcon_io5 expcon_io7 expcon_io9 expcon_io11 expcon_io13 expcon_io15 expcon_io20 expcon_io23 expcon_io26 expcon_io0 expcon_io2 expcon_io4 expcon_io6 expcon_io8 expcon_io10 expcon_io12 expcon_io14 expcon_io16 expcon_io17 expcon_io18 expcon_io19 expcon_io21 expcon_io22 expcon_io24 expcon_io25 expcon_io27 expcon_io28 hpe_resout# cardsel# cardsel# expcon_clkin expcon_clkout expcon_osc hpe_resout# bb3v3_io[11:0] bb3v3_io[11:0] expcon_3v3 expcon_io[45:0] bb3v3_clk0+ bb3v3_clk0- expcon_io39 expcon_io37 expcon_io35 expcon_io33 expcon_io31 expcon_io29 expcon_io30 expcon_io32 expcon_io34 expcon_io36 expcon_io38 expcon_2v5 expcon_osc expcon_clkin expcon_clkout expcon_3v3 expcon_io40 expcon_io41 expcon_io42 expcon_io43 expcon_io44 expcon_io45 bb3v3_io3 bb3v3_io2 bb3v3_io1 bb3v3_io0 bb3v3_io4 expcon_2v5 bb3v3_io5 bb3v3_io6 bb3v3_io7 bb3v3_io8 bb3v3_io9 bb3v3_io10 bb3v3_io11 bb2v5_io[7:0] bb2v5_io0 bb2v5_io[7:0] bb2v5_io1 bb2v5_io2 bb2v5_io3 bb2v5_io4 hscon_dat3+ hscon_dat3- hscon_dat1- hscon_dat0- hscon_dat0+ hscon_dat0- hscon_dat1+ hscon_dat1- hscon_dat2+ hscon_dat2- hscon_dat2- hscon_dat2+ hscon_dat3+ hscon_dat3- bb3v3_clk0- bb3v3_clk0+ hscon_dat1+ hscon_dat0+ hscon_dat4+ hscon_dat4- hscon_dat1+ hscon_dat1- hscon_dat2+ hscon_dat2- hscon_dat0+ hscon_dat0- hscon_dat3+ hscon_dat3- hscon_dat4+ hscon_dat4- hscon_dat4- hscon_dat4+ bb2v5_io5 bb2v5_io6 bb2v5_io7 vcc3v3 gnd gnd vcc3v3 gnd vcc2v5 gnd gnd vcc3v3 vcc5v0 vcc2v5 gnd_hs gnd_hs gnd gnd_hs cardsel# 2 expcon_clkin 2 expcon_clkout 2 expcon_osc 6 hpe_resout# 2,6,7,8 bb3v3_io[11:0] 2,3 expcon_io[45:0] 2,3 bb3v3_clk0+ 2 bb3v3_clk0- 2 bb2v5_io[7:0] 2 hscon_dat4+ 2 hscon_dat4- 2 hscon_dat1+ 2 hscon_dat1- 2 hscon_dat2+ 2 hscon_dat2- 2 hscon_dat0+ 2 hscon_dat0- 2 hscon_dat3+ 2 hscon_dat3- 2 : t e e h s : t c e j o r p authors: revision: created: last modified: ifw: of page c p x e _ 9 0 on_protoarea 12 9 offpage expansi on connector prototyping area (rm2.54) of fpga pin 2 removed for coding of expansion board lvds lvds connector for the lvds-pairs lvds lvds lvds tp09104 tp0935 tp0996 tp0912 tp0963 tp09124 tp0954 tp09117 tp0944 tp0908 tp09106 tp0936 tp0921 tp0964 tp0986 tp09125 r0901 0r00 1 2 tp0957 tp09115 tp0946 tp09107 tp09135 tp0926 tp0965 tp0985 tp09126 tp0955 tp0920 tp09116 tp0947 tp09108 tp0909 tp0975 tp09136 tp0925 tp0966 tp09129 tp0934 tp0956 tp09118 tp0948 tp0976 tp0998 tp09137 tp0969 tp0922 tp09127 tp0958 tp0903 x14 hdr20 12 34 5 6 78 910 11 12 13 14 15 16 17 18 19 20 tp09119 tp0938 tp0977 tp09133 tp0910 tp09138 tp0967 tp09128 tp0901 tp0959 tp0987 tp09120 tp0937 tp0923 tp0978 tp09141 tp0968 tp09130 tp0927 tp0960 tp0904 tp0988 tp09110 tp0981 tp0911 tp09139 tp0970 x12 hdr40 1 2 34 56 7 8 910 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 tp0924 tp09131 tp0928 tp0950 tp09121 tp0915 tp0989 tp0979 tp09140 tp0971 tp0999 tp09132 tp0929 tp0949 tp0990 r0904 10k0 1 2 tp0980 tp0914 tp09142 x13 hdr40 12 3 4 5 6 78 910 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 tp0939 tp0972 tp0916 tp09100 tp0905 tp09122 tp0930 tp0993 tp0982 tp09143 tp0940 tp0962 tp09109 tp09101 tp0933 tp0913 tp0991 tp0917 tp0983 tp0902 tp09111 tp09144 tp0941 tp0961 tp09102 tp0906 tp0931 tp0992 tp0984 tp0951 tp09112 tp09134 tp0942 tp09105 tp0918 r0902 0r00 1 2 tp0932 tp0994 tp0952 tp0974 tp0997 tp09113 tp0945 tp09103 tp0907 tp0995 tp09123 tp0953 tp0919 tp0973 tp09114 tp0943
42 latticemico32/dsp development board lattice semiconductor user? guide figure 20. 5 5 4 4 3 3 2 2 1 1 d d c c b b a a codec_sdin rlinein_x llinein_x rlinein_r codec_rlinein codec_llinein llinein_r codec_din codec_sdin codec_sclk codec_lrcin codec_bclk codec_mclk codec_rout codec_lout rlineout_x llineout_x codec_micbias codec_dout codec_lrcout micin_x codec_micin codec_sclk codec_din codec_cs# codec_bclk codec_lrcin codec_dout codec_mclk codec_lrcout vga_rd0 vga_gr0 vga_bl0 vga_rd1 vga_gr1 vga_bl1 vga_vsync vga_rd0 vga_rd1 vga_gr0 vga_bl0 vga_gr1 vga_hsync vga_bl1 vga_vsync vcc3v3_audio codec_cs# codec_mode codec_mode codec_mode vga_rd_x vga_gr_x vga_bl_x vga_hsync vcc3v3 gndp gnd gnd gnd gnd vcc3v3 gnd gnd gnd vcc3v3 vcc3v3 gndp gnd gnd codec_sdin 2 codec_sclk 2 codec_din 2 codec_cs# 2 codec_bclk 2 codec_lrcin 2 codec_dout 2 codec_mclk 2 codec_lrcout 2 vga_rd0 2 vga_rd1 2 vga_gr0 2 vga_gr1 2 vga_bl0 2 vga_hsync 2 vga_bl1 2 vga_vsync 2 codec_mode 2 : t e e h s : t c e j o r p authors: revision: created: last modified: ifw: of page 10_audio_vga 12 10 audio codec micin linein lineout vga interface offpage inter face mode 0 1 2-wire spi 10u0 c1011 47p0 c1005 470n c1004 r1007 4k70 12 r1005 4k70 12 r1018 270r r1002 100r 12 r1012 270r r1009 10k0 1 2 470n c1003 r1013 270r rj1002 nb_10k0 1 2 1u00 c1012 47p0 c1013 fb1001 blm18pg600sn1 12 r1019 10k0 1 2 nf_r nf_l shield x15a st-4235-3/3-n 5l 1l 4l 2l 1 1 r1014 270r 100n c1010 r1010 270r r1001 4k70 12 rj1001 10k0 1 2 100n c1008 r1015 270r nf_r nf_l shield x15b st-4235-3/3-n 5u 1u 4u 3l 4 4 x16 nb_hdr2 1 2 r1008 10k0 12 470n c1001 x19 con_dsub_15f 7 2 8 3 9 4 10 5 1 6 11 12 13 14 15 r1004 100r 1 2 470n c1002 100n c1009 r1016 270r r1006 4k70 12 10u0 c1007 tlv320aic23bipwr u1001 rout 13 agnd 15 xti/mclk 25 bvdd 1 rhpout 10 sdin 23 bclk 3 lout 12 micbias 17 lhpout 9 lrcin 5 dvdd 27 rlinein 19 clkout 2 dgnd 28 lrcout 7 xto 26 hpvdd 8 micin 18 sclk 24 hpgnd 11 llinein 20 din 4 vmid 16 mode 22 cs 21 avdd 14 dout 6 47p0 c1006 r1011 270r r1017 270r r1003 4k70 1 2
43 latticemico32/dsp development board lattice semiconductor user? guide figure 21. 5 5 4 4 3 3 2 2 1 1 d d c c b b a a pw_t1b_gate pw_sw2_l pw_vos2 pw_sw2 pw_boost2 pw_t2b_gate pw_t1a_gate pw_t2a_gate vcc_kld pw_boost1 pw_sw1 vos1 pw_sw1_l gndp vcc3v3 vcc5v0 vcc5v0 gnd_pwr vcc5v0 gnd gnd gnd_pwr gnd_pwr gnd gnd gnd_pwr gnd_pwr gnd_pwr gnd gnd_pwr gnd_pwr gnd_pwr gnd_pwr gnd_pwr gnd gnd gnd_pwr gnd_pwr gnd_pwr gnd gnd_pwr gndp vcc5v0 gnd gnd gnd gnd gnd gnd vcc1v2 vcc2v5 : t e e h s : t c e j o r p authors: revision: created: last modified: ifw: of page s r e w o p _ 1 1 upply 12 11 3.3v (1a) / 1.2v (2a) dc/dc-converter connect analog gnd to gnd on plane offpage c7343h 10v 20v c7343 lesr40 20v c7343 drill max 1a 1% 1% 3.3v gnd 1.2v 3.3v pg 1% 1% lesr40 max 2a 10v 10v c7343h place the parts c1103, c1105 and c1124 as close as possible to the pins of the u1101 extra analog gnd plane connected with 6vias to gnd on plane 2.5v/2.6v (2a) 2.5v set the jumper to 1-2 for 2.5v and to 3-2 for 2.6v (this is important for the ddr sdram module) % 1 % 1 1% max 2.4a 2.5v pg miscellaneous 10u0 c1129 r1119 39k0 1 2 l1101 33u0 + c1111 220u 100n c1116 nb_10n0 c1113 r1103 4k70 12 x17 kld-0202-a outside 1 opener 2 center 3 + c1106 47u0 drill1101 drill d1106 10mq040n 12 r1115 0r033 12 100n c1102 tp1102 test point 1 l1103 10u0 r1111 0r05 12 d1103 10mq040n 12 ld1102 led green 10u0 c1101 si6966dq t1101a 4 1 2 3 220p c1118 optional pad1102 artnr05281 ld1101 led green d1104 mbr0540lt1 1 2 nb_10n0 c1125 r1114 330r 12 + c1130 220u optional pad1101 artnr05281 optional pad1105 artnr05281 r1107 15k0 12 4p70 c1132 d1101 mbr0540lt1 1 2 si6966dq t1102a 4 1 2 3 r1108 15k0 12 100n c1124 si6966dq t1101b 5 8 7 6 r1112 47k0 12 d1102 10mq040n 12 optional pad1104 artnr05281 100n c1121 r1116 10r0 12 33p0 c1122 d1105 10mq040n 12 + c1107 47u0 s d g t1103 si3445dv 4 5 1 2 3 6 7 8 optional pad1103 artnr05281 1u00 c1134 r1113 15k0 12 tp1104 test point 1 r1117 42k2 1 2 10u0 c1110 10u0 c1131 l1102 100u0 33p0 c1123 100n c1103 optional artnr02296 jumper x18 hdr3 1 2 3 r1110 5r10 12 r1102 0r025 12 tp1103 test point 1 r1105 5r10 12 100n c1120 u1102 tps64203dbvt en 1 gnd 2 fb 3 sw 6 vin 5 isense 4 optional label01 label 100n c1105 10u0 c1104 u1101 ltc1628-ssop28 vin 24 boost1 25 sw1 26 tg1 27 bg1 23 ext_vcc 22 intvcc 21 freqset 5 sense1- 3 vos1 4 boost2 18 tg2 16 sw2 17 bg2 19 sense2+ 14 sense2- 13 vos2 12 sense1+ 2 fltcpl 28 fcb 7 3v3out 10 stbymd 6 run/ss1 1 run/ss2 15 ith1 8 ith2 11 sgnd 9 pgnd 20 + c1133 100u drill1104 drill 1n00 c1127 r1104 5k10 1 2 10u0 c1115 tp1101 test point 1 r1106 10k0 1 2 10u0 c1114 180p c1109 10n0 c1119 r1118 36k0 1 2 1n00 c1126 drill1103 drill 220p c1117 drill1102 drill si6966dq t1102b 5 8 7 6 1n00 c1112 180p c1128 1n00 c1108 r1120 100r 12
44 latticemico32/dsp development board lattice semiconductor user? guide appendix b. assembly diagram note: figures 23-26 provide an enlargement of each numbered section in figure 22. figure 22. assembly diagram 12 34
45 latticemico32/dsp development board lattice semiconductor user? guide figure 23. assembly diagram, section 1 detail
46 latticemico32/dsp development board lattice semiconductor user? guide figure 24. assembly diagram, section 2 detail
47 latticemico32/dsp development board lattice semiconductor user? guide figure 25. assembly diagram, section 3 detail
48 latticemico32/dsp development board lattice semiconductor user? guide figure 26. assembly diagram, section 4 detail

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